component

ADS4145IRGZT

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionads4145irgztfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

ADS4145IRGZT

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)

ADS4145IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRGND power_in Digital and output buffer ground; the exposed thermal pad is also connected to DRGND.
2 DRVDD power_in 1.8-V digital and output buffer supply (1.7 V to 1.9 V recommended).
3 OVR_SDOUT output Out-of-range indicator after reset when READOUT = 0; serial register readout output when READOUT = 1.
4 CLKOUTM output Differential output clock, complement (LVDS mode).
5 CLKOUTP output Differential output clock, true (LVDS mode).
6 DFS input Analog 4-level data format select pin that sets twos complement or offset binary data and the DDR LVDS or parallel CMOS output interface (see Table 5); set by a resistor divider with 10% tolerance resistors.
7 OE input Output buffer enable, active high; 0 V disables output data buffers and AVDD enables them; internal 180-kΩ pullup to DRVDD.
8 AVDD power_in 1.8-V analog power supply (1.7 V to 1.9 V recommended).
9 AGND power_in Analog ground.
10 CLKP input Differential clock input, true; sine-wave clock amplitude 0.2 V to 1.5 V, ac-coupled.
11 CLKM input Differential clock input, complement; used with CLKP as the differential sample clock pair.
12 AGND power_in Analog ground.
13 VCM output Outputs the 0.95-V common-mode voltage that can be used externally to bias the analog input pins.
14 AGND power_in Analog ground.
15 INP input Differential analog input, positive; 2 VPP differential full-scale input with common-mode of VCM ±0.05 V.
16 INM input Differential analog input, negative; 2 VPP differential full-scale input with common-mode of VCM ±0.05 V.
17 AGND power_in Analog ground.
18 AVDD power_in 1.8-V analog power supply (1.7 V to 1.9 V recommended).
19 AGND power_in Analog ground.
20 AVDD power_in 1.8-V analog power supply (1.7 V to 1.9 V recommended).
21 NC unconnected Do not connect.
22 AVDD power_in 1.8-V analog power supply (1.7 V to 1.9 V recommended).
23 RESERVED input Digital control pin reserved for future use.
24 AVDD power_in 1.8-V analog power supply (1.7 V to 1.9 V recommended).
25 AGND power_in Analog ground.
26 AVDD power_in 1.8-V analog power supply (1.7 V to 1.9 V recommended).
27 SEN input Serial interface enable when RESET is low; must be tied to AVDD when RESET is high (then usable as analog control); internal 180-kΩ pullup to AVDD.
28 SDATA input Serial interface data input when RESET is low; STANDBY control when RESET is high (logic high enters standby); internal 180-kΩ pulldown.
29 SCLK input Serial interface clock input when RESET is low; must be tied to ground when RESET is high; internal 180-kΩ pulldown.
30 RESET input Serial interface reset input; a high pulse longer than 10 ns resets registers to default; tie high to use the parallel control pins; internal 180-kΩ pulldown.
31 NC unconnected Do not connect.
32 NC unconnected Do not connect.
33 D0_D1_M output Differential output data D0 and D1 multiplexed, complement (DDR LVDS).
34 D0_D1_P output Differential output data D0 and D1 multiplexed, true (DDR LVDS).
35 DRVDD power_in 1.8-V digital and output buffer supply (1.7 V to 1.9 V recommended).
36 DRGND power_in Digital and output buffer ground.
37 D2_D3_M output Differential output data D2 and D3 multiplexed, complement (DDR LVDS).
38 D2_D3_P output Differential output data D2 and D3 multiplexed, true (DDR LVDS).
39 D4_D5_M output Differential output data D4 and D5 multiplexed, complement (DDR LVDS).
40 D4_D5_P output Differential output data D4 and D5 multiplexed, true (DDR LVDS).
41 D6_D7_M output Differential output data D6 and D7 multiplexed, complement (DDR LVDS).
42 D6_D7_P output Differential output data D6 and D7 multiplexed, true (DDR LVDS).
43 D8_D9_M output Differential output data D8 and D9 multiplexed, complement (DDR LVDS).
44 D8_D9_P output Differential output data D8 and D9 multiplexed, true (DDR LVDS).
45 D10_D11_M output Differential output data D10 and D11 multiplexed, complement (DDR LVDS).
46 D10_D11_P output Differential output data D10 and D11 multiplexed, true (DDR LVDS).
47 D12_D13_M output Differential output data D12 and D13 multiplexed, complement (DDR LVDS); 14-bit device pin.
48 D12_D13_P output Differential output data D12 and D13 multiplexed, true (DDR LVDS); 14-bit device pin.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Data Acquisition
Pins 49

CAD (KiCad official)

  • Symbol: ADS4145IRGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads4145irgzt-etched.step / ads4145irgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4145irgzt.step / ads4145irgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 e1046b38c80e73e5, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF