component

ADS4129IRGZR

Public Made by Adom

by adom

Texas Instruments Pre-ordered Chips, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsads4129irgzrfactory-2.0.0extractor-text

Verified ADS4129IRGZR

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS4129IRGZR · QFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 83-page datasheet
  • ✓distributor: lcsc C2862690, digikey ADS4129IRGZR-ND, mouser 595-ADS4129IRGZR
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-kn4wl7y7/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.80)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads4129irgzr.kicad_sym✓ ads4129irgzr.kicad_mod✓ ads4129irgzr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ads4129irgzr / README.md
History Download
Ray Publish 0.1.0 aa3b429 4d ago

ADS4129IRGZR

Texas Instruments · Pre-ordered Chips · QFN-48-EP(7x7)

ADS4129IRGZR from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRGND power_in Digital and output buffer ground; the PowerPAD is connected to DRGND.
2 DRVDD power_in 1.8V digital and output buffer supply.
3 OVR_SDOUT output Out-of-range indicator after reset (READOUT = 0); functions as the serial register readout pin when READOUT = 1.
4 CLKOUTM output Differential output clock, complement (LVDS mode).
5 CLKOUTP output Differential output clock, true (LVDS mode).
6 DFS input Analog 4-level data format select input that sets twos complement or offset binary output and the LVDS/CMOS output interface type, per Table 7 (tied to 0 V, AVDD, or divider voltages with 10% tolerance resistors).
7 OE input Output buffer enable input, active high, with an internal 180kΩ pull-up to DRVDD; 0 V disables the output data buffers and AVDD enables them.
8 AVDD power_in 1.8V analog power supply.
9 AGND power_in Analog ground.
10 CLKP input Differential clock input, positive.
11 CLKM input Differential clock input, negative.
12 AGND power_in Analog ground.
13 VCM output Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins.
14 AGND power_in Analog ground.
15 INP input Differential analog input, positive.
16 INM input Differential analog input, negative.
17 AGND power_in Analog ground.
18 AVDD power_in 1.8V analog power supply.
19 AGND power_in Analog ground.
20 AVDD power_in 1.8V analog power supply.
21 NC unconnected Not connected; do not connect.
22 AVDD power_in 1.8V analog power supply.
23 RESERVED input Digital control pin reserved for future use; it is a digital input.
24 AVDD power_in 1.8V analog power supply.
25 AGND power_in Analog ground.
26 AVDD power_in 1.8V analog power supply.
27 SEN input Serial interface enable input when RESET is low; when RESET is high, SEN has no function and should be tied to AVDD (internal 180kΩ pull-up to AVDD).
28 SDATA input Serial interface data input when RESET is low; when RESET is high it functions as the STANDBY control pin (Table 9), with an internal 180kΩ pull-down.
29 SCLK input Serial interface clock input when RESET is low; when RESET is high it has no function and should be tied to ground (internal 180kΩ pull-down).
30 RESET input Serial interface reset input; a high pulse initializes the registers in serial mode, and it must be tied high for parallel operation (internal 180kΩ pull-down).
31 NC unconnected Not connected; do not connect.
32 NC unconnected Not connected; do not connect.
33 NC unconnected Not connected; do not connect.
34 NC unconnected Not connected; do not connect.
35 DRVDD power_in 1.8V digital and output buffer supply.
36 DRGND power_in Digital and output buffer ground; the PowerPAD is connected to DRGND.
37 D0_D1_M output Differential LVDS output data D0 and D1 multiplexed, complement (standard swing 350mV with external 100Ω termination).
38 D0_D1_P output Differential LVDS output data D0 and D1 multiplexed, true (standard swing 350mV with external 100Ω termination).
39 D2_D3_M output Differential LVDS output data D2 and D3 multiplexed, complement (standard swing 350mV with external 100Ω termination).
40 D2_D3_P output Differential LVDS output data D2 and D3 multiplexed, true (standard swing 350mV with external 100Ω termination).
41 D4_D5_M output Differential LVDS output data D4 and D5 multiplexed, complement (standard swing 350mV with external 100Ω termination).
42 D4_D5_P output Differential LVDS output data D4 and D5 multiplexed, true (standard swing 350mV with external 100Ω termination).
43 D6_D7_M output Differential LVDS output data D6 and D7 multiplexed, complement (standard swing 350mV with external 100Ω termination).
44 D6_D7_P output Differential LVDS output data D6 and D7 multiplexed, true (standard swing 350mV with external 100Ω termination).
45 D8_D9_M output Differential LVDS output data D8 and D9 multiplexed, complement (standard swing 350mV with external 100Ω termination).
46 D8_D9_P output Differential LVDS output data D8 and D9 multiplexed, true (standard swing 350mV with external 100Ω termination).
47 D10_D11_M output Differential LVDS output data D10 and D11 multiplexed, complement (standard swing 350mV with external 100Ω termination).
48 D10_D11_P output Differential LVDS output data D10 and D11 multiplexed, true (standard swing 350mV with external 100Ω termination).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-48-EP(7x7)
Category Interface ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD Analog supply voltage AVDD 1.7 1.8 1.9 V 4
DRVDD Digital supply voltage DRVDD 1.7 1.8 1.9 V 4
Input common-mode voltage VCM -0.05 0.05 V 4
Maximum analog input frequency 400 MHz with 2VPP input amplitude 4
Maximum analog input frequency 800 MHz with 1VPP input amplitude 4
Input clock sample rate 20 80 MSPS Low-speed mode enabled 4
Input clock sample rate 80 250 MSPS Low-speed mode disabled 4
Input clock amplitude differential (VCLKP - VCLKM) 0.2 1.5 VPP Sine wave, ac-coupled 4
Input clock duty cycle 40 50 60 % Low-speed mode enabled 4
Input clock duty cycle 35 50 65 % Low-speed mode disabled 4
Maximum external load capacitance from each output pin to DRGND CLOAD 5 pF 4
Operating free-air temperature TA -40 85 °C 4
Supply voltage range, AVDD -0.3 2.1 V 3
Supply voltage range, DRVDD -0.3 2.1 V 3
Voltage between AGND and DRGND -0.3 0.3 V 3
Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 2.1 V 3
Voltage between DRVDD to AVDD (when DRVDD leads AVDD) 0 2.1 V 3
Voltage applied to input pins INP, INM (max printed as minimum(1.9, AVDD + 0.3)) -0.3 V 3
Voltage applied to input pins CLKP, CLKM, DFS, OE (max printed as AVDD + 0.3) -0.3 V 3
RESET, SCLK, SDATA, SEN voltage -0.3 3.9 V 3
Operating free-air temperature range, TA TA -40 85 °C 3
Operating junction temperature range, TJ TJ 125 °C 3
Storage temperature range, Tstg Tstg -65 150 °C 3
SNR (signal-to-noise ratio), LVDS SNR 65.8 69 dBFS fIN = 170MHz, LVDS 5
SINAD (signal-to-noise and distortion ratio), LVDS SINAD 65.5 68.7 dBFS fIN = 170MHz, LVDS 5
Spurious-free dynamic range SFDR 70 80 dBc fIN = 170MHz 5
Total harmonic distortion THD 69 79 dBc fIN = 170MHz 5
Second-harmonic distortion HD2 70 84 dBc fIN = 170MHz 5
Third-harmonic distortion HD3 70 80 dBc fIN = 170MHz 5
Worst spur (other than second and third harmonics) 75 88 dBc fIN = 170MHz 5
Differential nonlinearity DNL -0.95 0.2 2.5 LSBs fIN = 170MHz 5
Integrated nonlinearity INL 0.5 5 LSBs fIN = 170MHz 5
AC power-supply rejection ratio PSRR 30 dB For 100mVPP signal on AVDD supply, up to 10MHz 5
Differential input resistance (at dc) 1 MΩ see Figure 114 7
Offset error -15 2.5 15 mV 7
Gain error as a result of internal reference inaccuracy alone EGREF -2 2 %FS 7
Analog supply current IAVDD 99 113 mA 7
Output buffer supply current, standard LVDS swing (350mV) IDRVDD 59 72 mA LVDS interface with 100Ω external termination; Standard LVDS swing (350mV) 7
Global power-down 10 25 mW 7
High-level input voltage, RESET, SCLK, SDATA, SEN 1.3 V 8
Low-level input voltage, CMOS logic levels 0.4 V CMOS logic levels 8
High-level input voltage, OE 1.3 V OE only supports 1.8V CMOS logic levels 8
Low-level input voltage, OE 0.4 V 8
Low-level output voltage, CMOS interface 0 0.1 V 8
High-level output voltage, standard swing LVDS VODH 270 350 430 mV Standard swing LVDS, with external 100Ω termination 8
Low-level output voltage, standard swing LVDS VODL -430 -350 -270 mV Standard swing LVDS, with external 100Ω termination 8
Output common-mode voltage VOCM 0.85 1.05 1.25 V 8
Thermal resistance, junction-to-ambient θJA 29 °C/W 3
Thermal resistance, junction-to-board θJB 10 °C/W 3
Junction-to-top characterization parameter ψJT 0.3 °C/W 3
Junction-to-board characterization parameter ψJB 9 °C/W 3
Thermal resistance, junction-to-case (bottom) θJCbot 1.13 °C/W 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs ESD, human body model (HBM) 2 kV (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may 3

CAD (KiCad official)

  • Symbol: ADS4129IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads4129irgzr-etched.step / ads4129irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4129irgzr.step / ads4129irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (83 pp, sha256 74c5b7c59136a967, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF