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ADS4128IRGZT

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionads4128irgztfactory-2.0.0extractor-text

Verified ADS4128IRGZT

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS4128IRGZT · VQFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 58-page datasheet
  • ✓distributor: lcsc C2861271, digikey 296-30542-2-ND, mouser 595-ADS4128IRGZT
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-hcfi62su/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.55)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
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ADS4128IRGZT

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-48-EP(7x7)

ADS4128IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRGND power_in Digital and output buffer ground.
2 DRVDD power_in 1.8-V digital and output buffer supply.
3 OVR_SDOUT output Out-of-range indicator after reset when READOUT = 0, and serial register readout pin when READOUT = 1.
4 CLKOUTM output Differential output clock, negative (LVDS mode; unused pin in CMOS mode).
5 CLKOUTP output Differential output clock, positive (CMOS output clock CLKOUT in CMOS mode).
6 DFS input Data format select input that sets the data format (twos complement or offset binary) and the LVDS or CMOS output interface type; see Table 9.
7 OE input Output buffer enable input, active high, with internal 180-kΩ pull-up resistor to DRVDD.
8 AVDD power_in 1.8-V analog power supply.
9 AGND power_in Analog ground.
10 CLKP input Differential clock input, positive.
11 CLKM input Differential clock input, negative.
12 AGND power_in Analog ground.
13 VCM output Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins.
14 AGND power_in Analog ground.
15 INP input Differential analog input, positive.
16 INM input Differential analog input, negative.
17 AGND power_in Analog ground.
18 AVDD power_in 1.8-V analog power supply.
19 AGND power_in Analog ground.
20 AVDD power_in 1.8-V analog power supply.
21 NC unconnected Do not connect.
22 AVDD power_in 1.8-V analog power supply.
23 RESERVED input Digital control pin, reserved for future use.
24 AVDD power_in 1.8-V analog power supply.
25 AGND power_in Analog ground.
26 AVDD power_in 1.8-V analog power supply.
27 SEN input Serial interface enable input when RESET is low; when RESET is high it has no function and should be tied to AVDD; internal 180-kΩ pull-up resistor to AVDD.
28 SDATA input Serial interface data input when RESET is low, STANDBY control pin when RESET is high; internal 180-kΩ pull-down resistor.
29 SCLK input Serial interface clock input when RESET is low; when RESET is high it has no function and should be tied to ground; internal 180-kΩ pull-down resistor.
30 RESET input Serial interface reset input (high pulse initializes registers; tied high resets registers to defaults and enables parallel control), with internal 180-kΩ pull-down resistor.
31 NC unconnected Do not connect.
32 NC unconnected Do not connect.
33 NC unconnected Do not connect.
34 NC unconnected Do not connect.
35 DRVDD power_in 1.8-V digital and output buffer supply.
36 DRGND power_in Digital and output buffer ground.
37 D0_D1_M output Differential output data D0 and D1 multiplexed, complement (CMOS mode: D0).
38 D0_D1_P output Differential output data D0 and D1 multiplexed, true (CMOS mode: D1).
39 D2_D3_M output Differential output data D2 and D3 multiplexed, complement (CMOS mode: D2).
40 D2_D3_P output Differential output data D2 and D3 multiplexed, true (CMOS mode: D3).
41 D4_D5_M output Differential output data D4 and D5 multiplexed, complement (CMOS mode: D4).
42 D4_D5_P output Differential output data D4 and D5 multiplexed, true (CMOS mode: D5).
43 D6_D7_M output Differential output data D6 and D7 multiplexed, complement (CMOS mode: D6).
44 D6_D7_P output Differential output data D6 and D7 multiplexed, true (CMOS mode: D7).
45 D8_D9_M output Differential output data D8 and D9 multiplexed, complement (CMOS mode: D8).
46 D8_D9_P output Differential output data D8 and D9 multiplexed, true (CMOS mode: D9).
47 D10_D11_M output Differential output data D10 and D11 multiplexed, complement (CMOS mode: D10).
48 D10_D11_P output Differential output data D10 and D11 multiplexed, true (CMOS mode: D11).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category ADC/DAC/Data Conversion
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage AVDD -0.3 2.1 V 7
Digital supply voltage DRVDD -0.3 2.1 V 7
Voltage between AGND and DRGND -0.3 0.3 V 7
AVDD to DRVDD 0 2.1 V when AVDD leads DRVDD 7
DRVDD to AVDD 0 2.1 V when DRVDD leads AVDD 7
Voltage on INP, INM -0.3 V max printed as (1.9) AVDD + 0.3 7
Voltage on CLKP, CLKM, DFS, OE -0.3 V max printed AVDD + 0.3 7
Voltage on RESET, SCLK, SDATA, SEN -0.3 3.9 V 7
Operating free-air temperature TA -40 85 °C 7
Operating junction temperature TJ 125 °C 7
Storage temperature Tstg -65 150 °C 7
ESD HBM V(ESD) -1000 1000 V Human-body model, ANSI/ESDA/JEDEC JS-001 7
ESD CDM V(ESD) -500 500 V Charged-device model, JESD22-C101 7
Analog supply voltage AVDD 1.7 1.8 1.9 V 7
Digital supply voltage DRVDD 1.7 1.8 1.9 V 7
Differential input voltage range 2 VPP With 0-dB gain 7
Input common-mode voltage VCM -0.05 0.05 V VCM ± 0.05 V 7
Maximum analog input frequency 400 MHz With 2-VPP input amplitude 7
Maximum analog input frequency 800 MHz With 1-VPP input amplitude 7
Input clock sample rate 20 80 MSPS Low-speed mode enabled 7
Input clock sample rate 200 MSPS Low-speed mode disabled, > 80 7
Input clock amplitude, sine wave 0.2 1.5 VPP Sine wave, ac-coupled 7
Input clock duty cycle 40 50 60 % Low-speed mode enabled 8
Input clock duty cycle 35 50 65 % Low-speed mode disabled 8
Maximum external load capacitance CLOAD 5 pF from each output pin to DRGND 8
Differential load resistance RLOAD 100 Ω between LVDS output pairs 8
Operating free-air temperature TA -40 85 °C 8
Junction-to-ambient thermal resistance RθJA 27.9 °C/W RGZ (VQFN) 48 pins 8
Junction-to-case (top) thermal resistance RθJC(top) 15.1 °C/W 8
Junction-to-board thermal resistance RθJB 5.4 °C/W 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.7 °C/W 8
Signal-to-noise ratio, LVDS SNR 65.8 69 dBFS fIN = 170 MHz 9
Signal-to-noise and distortion ratio, LVDS SINAD 65.5 68.8 dBFS fIN = 170 MHz 9
Spurious-free dynamic range SFDR 70 85 dBc fIN = 170 MHz 9
Total harmonic distortion THD 69 83 dBc fIN = 170 MHz 9
Second-harmonic distortion HD2 70 85 dBc fIN = 170 MHz 9
Third-harmonic distortion HD3 70 86 dBc fIN = 170 MHz 9
Worst spur (other than second and third harmonics) 75 90 dBc fIN = 170 MHz 9
AC power-supply rejection ratio PSRR 30 dB For 50-mVPP signal on AVDD supply, up to 10 MHz 9
Differential nonlinearity DNL -0.95 0.2 1.6 LSBs fIN = 170 MHz 9
Integrated nonlinearity INL -5 0.5 5 LSBs fIN = 170 MHz 9
Offset error -15 2.5 15 mV 10
Gain error from internal reference alone EGREF -2 2 %FS 10
Gain error of channel alone EGCHAN -0.2 1 %FS 10
Analog supply current IAVDD 85 113 mA 10
Output buffer supply current, LVDS standard swing IDRVDD 55 72 mA 100-Ω external termination, Standard LVDS swing (350 mV) 10
Global power-down power 10 25 mW 10
High-level input voltage VIH 1.3 V RESET, SCLK, SDATA, SEN support 1.8-V and 3.3-V CMOS logic levels 11
High-level input voltage (OE) VIH 1.3 V OE only supports 1.8-V CMOS logic levels 11
Low-level input voltage VIL 0.4 V RESET, SCLK, SDATA, SEN support 1.8-V and 3.3-V CMOS logic levels 11
Low-level input voltage (OE) VIL 0.4 V OE only supports 1.8-V CMOS logic levels 11
Low-level output voltage, CMOS VOL 0 0.1 V 11
High-level output voltage, standard-swing LVDS VODH 270 350 430 mV With an external 100-Ω termination 11
Low-level output voltage, standard-swing LVDS VODL -430 -350 -270 mV With an external 100-Ω termination 11
Output common-mode voltage VOCM 0.85 1.05 1.25 V 11
Aperture delay tA 0.6 0.8 1.2 ns 12
Wakeup time from STANDBY 5 25 µs Time to valid data after coming out of STANDBY mode 12
Wakeup time from PDN GLOBAL 100 500 µs Time to valid data after coming out of PDN GLOBAL mode 12
Data setup time, DDR LVDS tSU 1.05 1.55 ns Data valid to zero-crossing of CLKOUTP 12
Data hold time, DDR LVDS tH 0.35 0.6 ns Zero-crossing of CLKOUTP to data becoming invalid 12
Clock propagation delay, DDR LVDS tPDI 3 4.2 5.4 ns 1 MSPS ≤ sampling frequency ≤ 200 MSPS 12
Output enable to data delay, LVDS tOE 50 100 ns Time to valid data after OE becomes active 12
Clock propagation delay, parallel CMOS tPDI 4 5.5 7 ns 1 MSPS ≤ sampling frequency ≤ 200 MSPS 12
Data valid time, parallel CMOS tDV 3.5 4.2 ns Time interval of valid data 12
Output enable to data delay, CMOS tOE 20 40 ns Time to valid data after OE becomes active 12

CAD (KiCad official)

  • Symbol: ADS4128IRGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads4128irgzt-etched.step / ads4128irgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4128irgzt.step / ads4128irgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 722a061e94269921, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF