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ADS4125IRGZR

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Texas Instruments Analog To Digital Converters (ADC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADS4125IRGZR

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)

ADS4125IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRGND power_in Digital and output buffer ground.
2 DRVDD power_in 1.8-V digital and output buffer supply.
3 OVR_SDOUT output Out-of-range indicator after reset when READOUT = 0, and serial register readout pin when READOUT = 1.
4 CLKOUTM output Differential output clock, complement (LVDS mode); unused pin in CMOS mode.
5 CLKOUTP output Differential output clock, true (LVDS mode); CMOS output clock (CLKOUT) in CMOS mode.
6 DFS input Data format select input that sets twos complement or offset binary and the LVDS or CMOS output interface type (4-level analog control, see Table 5).
7 OE input Output buffer enable input, active high, with internal 180-kΩ pullup resistor to DRVDD.
8 AVDD power_in 1.8-V analog power supply.
9 AGND power_in Analog ground.
10 CLKP input Differential clock input, true.
11 CLKM input Differential clock input, complement.
12 AGND power_in Analog ground.
13 VCM output Outputs the 0.95-V common-mode voltage that can be used externally to bias the analog input pins.
14 AGND power_in Analog ground.
15 INP input Differential analog input, positive.
16 INM input Differential analog input, negative.
17 AGND power_in Analog ground.
18 AVDD power_in 1.8-V analog power supply.
19 AGND power_in Analog ground.
20 AVDD power_in 1.8-V analog power supply.
21 NC unconnected Do not connect.
22 AVDD power_in 1.8-V analog power supply.
23 RESERVED input Digital control pin, reserved for future use.
24 AVDD power_in 1.8-V analog power supply.
25 AGND power_in Analog ground.
26 AVDD power_in 1.8-V analog power supply.
27 SEN input Serial interface enable input when RESET is low; when RESET is high it has no function and must be tied to AVDD; internal 180-kΩ pullup resistor to AVDD.
28 SDATA input Serial interface data input when RESET is low; when RESET is high it works as STANDBY control; internal 180-kΩ pulldown resistor.
29 SCLK input Serial interface clock input when RESET is low; when RESET is high it has no function and should be tied to ground; internal 180-kΩ pulldown resistor.
30 RESET input Serial interface reset input; a high pulse (or tying high) resets internal registers to defaults; internal 180-kΩ pulldown resistor.
31 NC unconnected Do not connect.
32 NC unconnected Do not connect.
33 NC unconnected Do not connect (ADS412x).
34 NC unconnected Do not connect (ADS412x).
35 DRVDD power_in 1.8-V digital and output buffer supply.
36 DRGND power_in Digital and output buffer ground.
37 D0_D1_M output Differential output data D0 and D1 multiplexed, complement (D0 in CMOS mode).
38 D0_D1_P output Differential output data D0 and D1 multiplexed, true (D1 in CMOS mode).
39 D2_D3_M output Differential output data D2 and D3 multiplexed, complement (D2 in CMOS mode).
40 D2_D3_P output Differential output data D2 and D3 multiplexed, true (D3 in CMOS mode).
41 D4_D5_M output Differential output data D4 and D5 multiplexed, complement (D4 in CMOS mode).
42 D4_D5_P output Differential output data D4 and D5 multiplexed, true (D5 in CMOS mode).
43 D6_D7_M output Differential output data D6 and D7 multiplexed, complement (D6 in CMOS mode).
44 D6_D7_P output Differential output data D6 and D7 multiplexed, true (D7 in CMOS mode).
45 D8_D9_M output Differential output data D8 and D9 multiplexed, complement (D8 in CMOS mode).
46 D8_D9_P output Differential output data D8 and D9 multiplexed, true (D9 in CMOS mode).
47 D10_D11_M output Differential output data D10 and D11 multiplexed, complement (D10 in CMOS mode).
48 D10_D11_P output Differential output data D10 and D11 multiplexed, true (D11 in CMOS mode).
49 DRGND power_in Exposed thermal pad, connected to DRGND (digital and output buffer ground).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Data Acquisition
Pins 49

CAD (KiCad official)

  • Symbol: ADS4125IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads4125irgzr-etched.step / ads4125irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4125irgzr.step / ads4125irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 e1046b38c80e73e5, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF