# ADS1602IPFBT

**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-48(7x7)

ADS1602IPFBT from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground. |
| 2 | AVDD | power_in | Analog supply; AVDD to AGND absolute maximum is -0.3 to +6 V. |
| 3 | AGND | power_in | Analog ground. |
| 4 | AINN | input | Negative analog input; the differential input voltage is AINP - AINN and absolute input voltage is referenced to AGND. |
| 5 | AINP | input | Positive analog input; the differential input voltage is AINP - AINN and absolute input voltage is referenced to AGND. |
| 6 | AGND | power_in | Analog ground. |
| 7 | AVDD | power_in | Analog supply; AVDD to AGND absolute maximum is -0.3 to +6 V. |
| 8 | RBIAS | passive | Terminal for external analog bias setting resistor; power dissipation is set by this external resistor. |
| 9 | AGND | power_in | Analog ground. |
| 10 | AVDD | power_in | Analog supply; AVDD to AGND absolute maximum is -0.3 to +6 V. |
| 11 | AGND | power_in | Analog ground. |
| 12 | AVDD | power_in | Analog supply; AVDD to AGND absolute maximum is -0.3 to +6 V. |
| 13 | REFEN | input | Active-low internal reference enable with an internal 170 kΩ pull-down resistor to DGND. |
| 14 | NC | unconnected | Do not connect; this terminal must be left unconnected. |
| 15 | RPULLUP | input | Digital input that is pulled up to DVDD through a 10 kΩ resistor (see Figure 53). |
| 16 | NC | unconnected | Do not connect; this terminal must be left unconnected. |
| 17 | PD | input | Active-low power-down of all circuitry, with an internal 170 kΩ pull-up resistor to DGND. |
| 18 | DVDD | power_in | Digital supply; DVDD to DGND absolute maximum is -0.3 to +3.6 V and 2.7 V to 3.6 V in the timing conditions. |
| 19 | DGND | power_in | Digital ground. |
| 20 | SYNC | input | Synchronization control input used for simultaneous sampling with multiple ADS1602s. |
| 21 | OTR | output | Digital output that indicates the analog input signal is out of range. |
| 22 | DGND | power_in | Digital ground. |
| 23 | DVDD | power_in | Digital supply; DVDD to DGND absolute maximum is -0.3 to +3.6 V and 2.7 V to 3.6 V in the timing conditions. |
| 24 | NC | unconnected | Do not connect; this terminal must be left unconnected. |
| 25 | NC | unconnected | Do not connect; this terminal must be left unconnected. |
| 26 | NC | unconnected | Do not connect; this terminal must be left unconnected. |
| 27 | SCLK | output | Complementary serial clock output (complement of pin 28). |
| 28 | SCLK | output | Serial clock output. |
| 29 | DOUT | output | Complementary data output (complement of pin 30). |
| 30 | DOUT | output | Data output. |
| 31 | FSO | output | Complementary frame synchronization output (complement of pin 32). |
| 32 | FSO | output | Frame synchronization output. |
| 33 | DGND | power_in | Digital ground. |
| 34 | DVDD | power_in | Digital supply; DVDD to DGND absolute maximum is -0.3 to +3.6 V and 2.7 V to 3.6 V in the timing conditions. |
| 35 | NC | unconnected | Do not connect; this terminal must be left unconnected. |
| 36 | DGND | power_in | Digital ground. |
| 37 | IOVDD | power_in | Digital I/O supply; IOVDD to DGND absolute maximum is -0.3 to +6 V and 2.7 V to 5.25 V in the timing conditions. |
| 38 | DGND | power_in | Digital ground. |
| 39 | AGND | power_in | Analog ground. |
| 40 | CLK | input | Clock input; the clock period (tC) is at least 25 ns. |
| 41 | AGND | power_in | Analog ground. |
| 42 | AVDD | power_in | Analog supply; AVDD to AGND absolute maximum is -0.3 to +6 V. |
| 43 | VCAP | passive | Terminal for external bypass capacitor connection to the internal bias voltage. |
| 44 | VREFN | passive | Negative reference voltage. |
| 45 | VREFN | passive | Negative reference voltage. |
| 46 | VMID | passive | Midpoint voltage. |
| 47 | VREFP | passive | Positive reference voltage. |
| 48 | VREFP | passive | Positive reference voltage. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-48(7x7) |
| Category | Data Acquisition |
| Pins | 48 |

## CAD (KiCad official)

- Symbol: `ADS1602IPFBT`
- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`
- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `ads1602ipfbt-etched.step` / `ads1602ipfbt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1602ipfbt.step` / `ads1602ipfbt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1602) (31 pp, sha256 `260bd18b0df99555`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ads1602ipfbt-datasheet.pdf)