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ADS131M08QPBSRQ1

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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS131M08QPBSRQ1

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(5x5)

ADS131M08QPBSRQ1 from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN2P input Positive analog input 2; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
2 AIN2N input Negative analog input 2; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
3 AIN3N input Negative analog input 3; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
4 AIN3P input Positive analog input 3; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
5 AIN4P input Positive analog input 4; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
6 AIN4N input Negative analog input 4; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
7 AIN5N input Negative analog input 5; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
8 AIN5P input Positive analog input 5; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
9 AIN6P input Positive analog input 6; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
10 AIN6N input Negative analog input 6; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
11 AIN7N input Negative analog input 7; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
12 AIN7P input Positive analog input 7; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
13 AGND power_in Analog ground; AGND to DGND must stay within -0.3 V to 0.3 V.
14 REFIN input External reference voltage input; reference input voltage is 1.1 V to 1.3 V, and no capacitance may be placed on REFIN when current-detect mode is used.
15 AVDD power_in Analog supply, 2.7 V to 3.6 V AVDD to AGND in normal operating modes; connect a 1-µF capacitor to AGND.
16 SYNC/RESET input Conversion synchronization or system reset input, active low; it must not be toggled asynchronously to CLKIN.
17 CS input Chip select input, active low; digital input voltage is limited to DGND to DVDD.
18 DRDY output Data-ready output, active low; it falls when new conversion data are available.
19 SCLK input Serial data clock input; digital input voltage is limited to DGND to DVDD.
20 DOUT output Serial data output; it stays high impedance while CS is high, allowing DOUT lines to be shared between devices.
21 DIN input Serial data input; digital input voltage is limited to DGND to DVDD.
22 XTAL2 output Crystal oscillator excitation output; see the Clocking and Power Modes section for the clocking scheme.
23 XTAL1/CLKIN input Main clock input or crystal oscillator input; external clock frequency is 0.3 MHz minimum and 8.192 MHz nominal in high-resolution mode, with 40% to 60% duty cycle.
24 CAP power_out Digital LDO regulator output; connect a 220-nF capacitor to DGND.
25 DGND power_in Digital ground; AGND to DGND must stay within -0.3 V to 0.3 V.
26 DVDD power_in Digital I/O supply, 2.7 V to 3.6 V DVDD to DGND (1.65 V to 2 V when DVDD is shorted to CAP); connect a 1-µF capacitor to DGND.
27 NC unconnected Not internally connected; leave unconnected or connect to AGND.
28 AGND power_in Analog ground; AGND to DGND must stay within -0.3 V to 0.3 V.
29 AIN0P input Positive analog input 0; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
30 AIN0N input Negative analog input 0; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
31 AIN1N input Negative analog input 1; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.
32 AIN1P input Positive analog input 1; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(5x5)
Category Data Acquisition
Pins 32

CAD (KiCad official)

  • Symbol: ADS131M08QPBSRQ1
  • Footprint: Package_QFP:TQFP-32_5x5mm_P0.5mm
  • 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ads131m08qpbsrq1-etched.step / ads131m08qpbsrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads131m08qpbsrq1.step / ads131m08qpbsrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (103 pp, sha256 704a7f192660fbc2, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF