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ADS131M08QPBSRQ1
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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+68@@ -0,0 +1,68 @@+# ADS131M08QPBSRQ1++**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-32(5x5)++ADS131M08QPBSRQ1 from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AIN2P | input | Positive analog input 2; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 2 | AIN2N | input | Negative analog input 2; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 3 | AIN3N | input | Negative analog input 3; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 4 | AIN3P | input | Positive analog input 3; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 5 | AIN4P | input | Positive analog input 4; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 6 | AIN4N | input | Negative analog input 4; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 7 | AIN5N | input | Negative analog input 5; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 8 | AIN5P | input | Positive analog input 5; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 9 | AIN6P | input | Positive analog input 6; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 10 | AIN6N | input | Negative analog input 6; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 11 | AIN7N | input | Negative analog input 7; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 12 | AIN7P | input | Positive analog input 7; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 13 | AGND | power_in | Analog ground; AGND to DGND must stay within -0.3 V to 0.3 V. |+| 14 | REFIN | input | External reference voltage input; reference input voltage is 1.1 V to 1.3 V, and no capacitance may be placed on REFIN when current-detect mode is used. |+| 15 | AVDD | power_in | Analog supply, 2.7 V to 3.6 V AVDD to AGND in normal operating modes; connect a 1-µF capacitor to AGND. |+| 16 | SYNC/RESET | input | Conversion synchronization or system reset input, active low; it must not be toggled asynchronously to CLKIN. |+| 17 | CS | input | Chip select input, active low; digital input voltage is limited to DGND to DVDD. |+| 18 | DRDY | output | Data-ready output, active low; it falls when new conversion data are available. |+| 19 | SCLK | input | Serial data clock input; digital input voltage is limited to DGND to DVDD. |+| 20 | DOUT | output | Serial data output; it stays high impedance while CS is high, allowing DOUT lines to be shared between devices. |+| 21 | DIN | input | Serial data input; digital input voltage is limited to DGND to DVDD. |+| 22 | XTAL2 | output | Crystal oscillator excitation output; see the Clocking and Power Modes section for the clocking scheme. |+| 23 | XTAL1/CLKIN | input | Main clock input or crystal oscillator input; external clock frequency is 0.3 MHz minimum and 8.192 MHz nominal in high-resolution mode, with 40% to 60% duty cycle. |+| 24 | CAP | power_out | Digital LDO regulator output; connect a 220-nF capacitor to DGND. |+| 25 | DGND | power_in | Digital ground; AGND to DGND must stay within -0.3 V to 0.3 V. |+| 26 | DVDD | power_in | Digital I/O supply, 2.7 V to 3.6 V DVDD to DGND (1.65 V to 2 V when DVDD is shorted to CAP); connect a 1-µF capacitor to DGND. |+| 27 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |+| 28 | AGND | power_in | Analog ground; AGND to DGND must stay within -0.3 V to 0.3 V. |+| 29 | AIN0P | input | Positive analog input 0; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 30 | AIN0N | input | Negative analog input 0; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 31 | AIN1N | input | Negative analog input 1; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |+| 32 | AIN1P | input | Positive analog input 1; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-32(5x5) |+| Category | Data Acquisition |+| Pins | 32 |++## CAD (KiCad official)++- Symbol: `ADS131M08QPBSRQ1`+- Footprint: `Package_QFP:TQFP-32_5x5mm_P0.5mm`+- 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `ads131m08qpbsrq1-etched.step` / `ads131m08qpbsrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads131m08qpbsrq1.step` / `ads131m08qpbsrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600663322114990080) (103 pp, sha256 `704a7f192660fbc2`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads131m08qpbsrq1-datasheet.pdf)
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absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "2",+ "name": "AIN2N",+ "type": "input",+ "description": "Negative analog input 2; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "3",+ "name": "AIN3N",+ "type": "input",+ "description": "Negative analog input 3; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "4",+ "name": "AIN3P",+ "type": "input",+ "description": "Positive analog input 3; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "5",+ "name": "AIN4P",+ "type": "input",+ "description": "Positive analog input 4; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "6",+ "name": "AIN4N",+ "type": "input",+ "description": "Negative analog input 4; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "7",+ "name": "AIN5N",+ "type": "input",+ "description": "Negative analog input 5; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "8",+ "name": "AIN5P",+ "type": "input",+ "description": "Positive analog input 5; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "9",+ "name": "AIN6P",+ "type": "input",+ "description": "Positive analog input 6; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "10",+ "name": "AIN6N",+ "type": "input",+ "description": "Negative analog input 6; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "11",+ "name": "AIN7N",+ "type": "input",+ "description": "Negative analog input 7; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "12",+ "name": "AIN7P",+ "type": "input",+ "description": "Positive analog input 7; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "13",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; AGND to DGND must stay within -0.3 V to 0.3 V."+ },+ {+ "number": "14",+ "name": "REFIN",+ "type": "input",+ "description": "External reference voltage input; reference input voltage is 1.1 V to 1.3 V, and no capacitance may be placed on REFIN when current-detect mode is used."+ },+ {+ "number": "15",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply, 2.7 V to 3.6 V AVDD to AGND in normal operating modes; connect a 1-µF capacitor to AGND."+ },+ {+ "number": "16",+ "name": "SYNC/RESET",+ "type": "input",+ "description": "Conversion synchronization or system reset input, active low; it must not be toggled asynchronously to CLKIN."+ },+ {+ "number": "17",+ "name": "CS",+ "type": "input",+ "description": "Chip select input, active low; digital input voltage is limited to DGND to DVDD."+ },+ {+ "number": "18",+ "name": "DRDY",+ "type": "output",+ "description": "Data-ready output, active low; it falls when new conversion data are available."+ },+ {+ "number": "19",+ "name": "SCLK",+ "type": "input",+ "description": "Serial data clock input; digital input voltage is limited to DGND to DVDD."+ },+ {+ "number": "20",+ "name": "DOUT",+ "type": "output",+ "description": "Serial data output; it stays high impedance while CS is high, allowing DOUT lines to be shared between devices."+ },+ {+ "number": "21",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input; digital input voltage is limited to DGND to DVDD."+ },+ {+ "number": "22",+ "name": "XTAL2",+ "type": "output",+ "description": "Crystal oscillator excitation output; see the Clocking and Power Modes section for the clocking scheme."+ },+ {+ "number": "23",+ "name": "XTAL1/CLKIN",+ "type": "input",+ "description": "Main clock input or crystal oscillator input; external clock frequency is 0.3 MHz minimum and 8.192 MHz nominal in high-resolution mode, with 40% to 60% duty cycle."+ },+ {+ "number": "24",+ "name": "CAP",+ "type": "power_out",+ "description": "Digital LDO regulator output; connect a 220-nF capacitor to DGND."+ },+ {+ "number": "25",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground; AGND to DGND must stay within -0.3 V to 0.3 V."+ },+ {+ "number": "26",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O supply, 2.7 V to 3.6 V DVDD to DGND (1.65 V to 2 V when DVDD is shorted to CAP); connect a 1-µF capacitor to DGND."+ },+ {+ "number": "27",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; leave unconnected or connect to AGND."+ },+ {+ "number": "28",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; AGND to DGND must stay within -0.3 V to 0.3 V."+ },+ {+ "number": "29",+ "name": "AIN0P",+ "type": "input",+ "description": "Positive analog input 0; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "30",+ "name": "AIN0N",+ "type": "input",+ "description": "Negative analog input 0; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "31",+ "name": "AIN1N",+ "type": "input",+ "description": "Negative analog input 1; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ },+ {+ "number": "32",+ "name": "AIN1P",+ "type": "input",+ "description": "Positive analog input 1; absolute input voltage is AGND - 1.3 V to AVDD for gains 1, 2 and 4, and AGND - 1.3 V to AVDD - 1.8 V for gains 8 to 128."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers, names and I/O descriptions come from Table 5-1 and Figure 5-1 (PBS 32-pin TQFP top view; KiCad type mapping was a judgment call where the datasheet gives only a generic label: AIN pins are ; Voltage limits in the pin descriptions come from Recommended Operating Conditions (page 6) and Absol"+ ],+ "pages_sent": 16,+ "cost_usd": 0.0993,+ "at": "2026-10-08T18:21:45"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600663322114990080",+ "pages": 103,+ "sha256": "704a7f192660fbc2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 32,+ "described": 32,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads131m08qpbsrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.96,+ 6.96,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dbeb9734a550a54251833acc96c8a6b8ace70cf4018d5aedfd34347361ae664",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads131m08qpbsrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.96,+ 6.96,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "013dc7c12df15758ae8c754c74fbcec07ada0cfb26a765d86ab6c5c90a07d22f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}