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ADS131M06QPBSRQ1
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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADS131M06QPBSRQ1
Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(5x5)
ADS131M06QPBSRQ1 from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN2P | input | Positive analog input of channel 2; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 2 | AIN2N | input | Negative analog input of channel 2; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 3 | AIN3N | input | Negative analog input of channel 3; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 4 | AIN3P | input | Positive analog input of channel 3; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 5 | AIN4P | input | Positive analog input of channel 4; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 6 | AIN4N | input | Negative analog input of channel 4; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 7 | AIN5N | input | Negative analog input of channel 5; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 8 | AIN5P | input | Positive analog input of channel 5; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 9 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 10 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 11 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 12 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 13 | AGND | power_in | Analog ground; AGND to DGND must be within -0.3 V to 0.3 V. |
| 14 | REFIN | input | External reference voltage input, specified 1.1 V to 1.3 V (1.25 V nominal); do not place any capacitance on REFIN when current-detect mode is used. |
| 15 | AVDD | power_in | Analog supply, 2.7 V to 3.6 V to AGND in normal operating modes (2.4 V minimum in standby and current-detect modes); decouple with a 1-µF capacitor to AGND. |
| 16 | SYNC/RESET | input | Conversion synchronization or system reset input, active low; it must be toggled synchronously to CLKIN. |
| 17 | CS | input | Chip select input, active low. |
| 18 | DRDY | output | Data-ready output, active low, signaling that new conversion data are available. |
| 19 | SCLK | input | Serial data clock input for the serial interface. |
| 20 | DOUT | output | Serial data output; high impedance when CS is high so that DOUT lines can be shared between devices. |
| 21 | DIN | input | Serial data input for the serial interface. |
| 22 | XTAL2 | output | Crystal oscillator excitation output; used only when the internal oscillator is driven by a crystal. |
| 23 | XTAL1/CLKIN | input | Main clock input (CLKIN) or crystal oscillator input (XTAL1); the external clock must be free of overshoot and glitches, with frequency limits given in Recommended Operating Conditions. |
| 24 | CAP | output | Output of the digital LDO regulator (1.8 V core); requires a 220-nF capacitor to DGND when DVDD > 2.7 V. |
| 25 | DGND | power_in | Digital ground; DVDD to DGND must be between -0.3 V and 3.9 V in absolute maximum ratings. |
| 26 | DVDD | power_in | Digital I/O supply, 2.7 V to 3.6 V to DGND; decouple with a 1-µF capacitor to DGND. |
| 27 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 28 | AGND | power_in | Analog ground; AGND to DGND must be within -0.3 V to 0.3 V. |
| 29 | AIN0P | input | Positive analog input of channel 0; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 30 | AIN0N | input | Negative analog input of channel 0; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 31 | AIN1N | input | Negative analog input of channel 1; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 32 | AIN1P | input | Positive analog input of channel 1; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-32(5x5) |
| Category | Data Acquisition |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
ADS131M06QPBSRQ1 - Footprint:
Package_QFP:TQFP-32_5x5mm_P0.5mm - 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
ads131m06qpbsrq1-etched.step/ads131m06qpbsrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads131m06qpbsrq1.step/ads131m06qpbsrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (95 pp, sha256
b4fe4c13aa9c20d5, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADS131M06QPBSRQ1
**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-32(5x5)
ADS131M06QPBSRQ1 from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN2P | input | Positive analog input of channel 2; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 2 | AIN2N | input | Negative analog input of channel 2; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 3 | AIN3N | input | Negative analog input of channel 3; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 4 | AIN3P | input | Positive analog input of channel 3; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 5 | AIN4P | input | Positive analog input of channel 4; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 6 | AIN4N | input | Negative analog input of channel 4; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 7 | AIN5N | input | Negative analog input of channel 5; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 8 | AIN5P | input | Positive analog input of channel 5; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 9 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 10 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 11 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 12 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 13 | AGND | power_in | Analog ground; AGND to DGND must be within -0.3 V to 0.3 V. |
| 14 | REFIN | input | External reference voltage input, specified 1.1 V to 1.3 V (1.25 V nominal); do not place any capacitance on REFIN when current-detect mode is used. |
| 15 | AVDD | power_in | Analog supply, 2.7 V to 3.6 V to AGND in normal operating modes (2.4 V minimum in standby and current-detect modes); decouple with a 1-µF capacitor to AGND. |
| 16 | SYNC/RESET | input | Conversion synchronization or system reset input, active low; it must be toggled synchronously to CLKIN. |
| 17 | CS | input | Chip select input, active low. |
| 18 | DRDY | output | Data-ready output, active low, signaling that new conversion data are available. |
| 19 | SCLK | input | Serial data clock input for the serial interface. |
| 20 | DOUT | output | Serial data output; high impedance when CS is high so that DOUT lines can be shared between devices. |
| 21 | DIN | input | Serial data input for the serial interface. |
| 22 | XTAL2 | output | Crystal oscillator excitation output; used only when the internal oscillator is driven by a crystal. |
| 23 | XTAL1/CLKIN | input | Main clock input (CLKIN) or crystal oscillator input (XTAL1); the external clock must be free of overshoot and glitches, with frequency limits given in Recommended Operating Conditions. |
| 24 | CAP | output | Output of the digital LDO regulator (1.8 V core); requires a 220-nF capacitor to DGND when DVDD > 2.7 V. |
| 25 | DGND | power_in | Digital ground; DVDD to DGND must be between -0.3 V and 3.9 V in absolute maximum ratings. |
| 26 | DVDD | power_in | Digital I/O supply, 2.7 V to 3.6 V to DGND; decouple with a 1-µF capacitor to DGND. |
| 27 | NC | unconnected | Not internally connected; leave unconnected or connect to AGND. |
| 28 | AGND | power_in | Analog ground; AGND to DGND must be within -0.3 V to 0.3 V. |
| 29 | AIN0P | input | Positive analog input of channel 0; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 30 | AIN0N | input | Negative analog input of channel 0; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 31 | AIN1N | input | Negative analog input of channel 1; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
| 32 | AIN1P | input | Positive analog input of channel 1; absolute input voltage must stay between AGND - 1.3 V and AVDD for gains 1, 2, and 4 (AVDD - 1.8 V upper limit for gains 8 to 128). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-32(5x5) |
| Category | Data Acquisition |
| Pins | 32 |
## CAD (KiCad official)
- Symbol: `ADS131M06QPBSRQ1`
- Footprint: `Package_QFP:TQFP-32_5x5mm_P0.5mm`
- 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `ads131m06qpbsrq1-etched.step` / `ads131m06qpbsrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads131m06qpbsrq1.step` / `ads131m06qpbsrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600395237923426304) (95 pp, sha256 `b4fe4c13aa9c20d5`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ads131m06qpbsrq1-datasheet.pdf)