component
ADS131M04IPWR
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# ADS131M04IPWR++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-20++ADS131M04IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AVDD | power_in | Analog supply voltage, 2.7 V to 3.6 V, requires 1-µF bypass capacitor to AGND. |+| 2 | AGND | power_in | Analog ground reference. |+| 3 | AIN0P | input | Positive differential analog input 0, accepts voltage range AGND − 1.3 V to AVDD. |+| 4 | AIN0N | input | Negative differential analog input 0, accepts voltage range AGND − 1.3 V to AVDD. |+| 5 | AIN1N | input | Negative differential analog input 1, accepts voltage range AGND − 1.3 V to AVDD. |+| 6 | AIN1P | input | Positive differential analog input 1, accepts voltage range AGND − 1.3 V to AVDD. |+| 7 | AIN2P | input | Positive differential analog input 2, accepts voltage range AGND − 1.3 V to AVDD. |+| 8 | AIN2N | input | Negative differential analog input 2, accepts voltage range AGND − 1.3 V to AVDD. |+| 9 | AIN3N | input | Negative differential analog input 3, accepts voltage range AGND − 1.3 V to AVDD. |+| 10 | AIN3P | input | Positive differential analog input 3, accepts voltage range AGND − 1.3 V to AVDD. |+| 11 | SYNC/RESET | input | Active-low digital input for synchronization (pulse 1-2047 tCLKIN) or device reset (pulse ≥2048 tCLKIN). |+| 12 | CS | input | Chip select, active-low digital input for SPI slave selection. |+| 13 | DRDY | output | Data ready, active-low digital output indicating new ADC conversion data available. |+| 14 | SCLK | input | Serial clock digital input for SPI interface with 40-64 ns period. |+| 15 | DOUT | output | Serial data output for SPI interface, transitions on SCLK rising edges when CS is low. |+| 16 | DIN | input | Serial data input for SPI interface, latches commands and register data on SCLK falling edges when CS is low. |+| 17 | CLKIN | input | Master clock input, 0.3-8.192 MHz for high-resolution mode, must toggle continuously during normal operation. |+| 18 | CAP | power_out | Digital LDO regulator output for internal 1.8 V core voltage, requires 220-nF bypass capacitor to DGND. |+| 19 | DGND | power_in | Digital ground reference. |+| 20 | DVDD | power_in | Digital supply voltage, 2.7 V to 3.6 V (or 1.65-2 V if CAP tied to DVDD), requires 1-µF bypass capacitor to DGND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Data Acquisition |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `ADS131M04IPWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `ads131m04ipwr-etched.step` / `ads131m04ipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads131m04ipwr.step` / `ads131m04ipwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/ds/symlink/ads131m04.pdf) (105 pp, sha256 `cc5bfca62f8b1b0d`, retrieved 2026-09-24, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads131m04ipwr-datasheet.pdf)
page.jsonadded+213@@ -0,0 +1,213 @@+{+ "slug": "ads131m04ipwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads131m04ipwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads131m04ipwr.kicad_sym",+ "ads131m04ipwr.kicad_mod",+ "ads131m04ipwr.glb",+ "ads131m04ipwr.step",+ "ads131m04ipwr.lbr",+ "docs/hero.png",+ "docs/ads131m04ipwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADS131M04IPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/ds/symlink/ads131m04.pdf",+ "parts": {+ "symbol": "ads131m04ipwr.kicad_sym",+ "footprint": "ads131m04ipwr.kicad_mod",+ "model_3d": "ads131m04ipwr-etched.glb",+ "model_3d_plain": "ads131m04ipwr.glb",+ "model_3d_step": "ads131m04ipwr-etched.step",+ "model_3d_step_plain": "ads131m04ipwr.step",+ "lbr": "ads131m04ipwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2862562"+ },+ "pins": [+ {+ "number": "1",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage, 2.7 V to 3.6 V, requires 1-µF bypass capacitor to AGND."+ },+ {+ "number": "2",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference."+ },+ {+ "number": "3",+ "name": "AIN0P",+ "type": "input",+ "description": "Positive differential analog input 0, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "4",+ "name": "AIN0N",+ "type": "input",+ "description": "Negative differential analog input 0, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "5",+ "name": "AIN1N",+ "type": "input",+ "description": "Negative differential analog input 1, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "6",+ "name": "AIN1P",+ "type": "input",+ "description": "Positive differential analog input 1, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "7",+ "name": "AIN2P",+ "type": "input",+ "description": "Positive differential analog input 2, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "8",+ "name": "AIN2N",+ "type": "input",+ "description": "Negative differential analog input 2, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "9",+ "name": "AIN3N",+ "type": "input",+ "description": "Negative differential analog input 3, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "10",+ "name": "AIN3P",+ "type": "input",+ "description": "Positive differential analog input 3, accepts voltage range AGND − 1.3 V to AVDD."+ },+ {+ "number": "11",+ "name": "SYNC/RESET",+ "type": "input",+ "description": "Active-low digital input for synchronization (pulse 1-2047 tCLKIN) or device reset (pulse ≥2048 tCLKIN)."+ },+ {+ "number": "12",+ "name": "CS",+ "type": "input",+ "description": "Chip select, active-low digital input for SPI slave selection."+ },+ {+ "number": "13",+ "name": "DRDY",+ "type": "output",+ "description": "Data ready, active-low digital output indicating new ADC conversion data available."+ },+ {+ "number": "14",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock digital input for SPI interface with 40-64 ns period."+ },+ {+ "number": "15",+ "name": "DOUT",+ "type": "output",+ "description": "Serial data output for SPI interface, transitions on SCLK rising edges when CS is low."+ },+ {+ "number": "16",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input for SPI interface, latches commands and register data on SCLK falling edges when CS is low."+ },+ {+ "number": "17",+ "name": "CLKIN",+ "type": "input",+ "description": "Master clock input, 0.3-8.192 MHz for high-resolution mode, must toggle continuously during normal operation."+ },+ {+ "number": "18",+ "name": "CAP",+ "type": "power_out",+ "description": "Digital LDO regulator output for internal 1.8 V core voltage, requires 220-nF bypass capacitor to DGND."+ },+ {+ "number": "19",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground reference."+ },+ {+ "number": "20",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply voltage, 2.7 V to 3.6 V (or 1.65-2 V if CAP tied to DVDD), requires 1-µF bypass capacitor to DGND."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 105,+ "cost_usd": 0.8671,+ "at": "2026-09-24T09:05:22"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/ds/symlink/ads131m04.pdf",+ "pages": 105,+ "sha256": "cc5bfca62f8b1b0d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}