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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS131M04IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-20

ADS131M04IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	Analog supply voltage, 2.7 V to 3.6 V, requires 1-µF bypass capacitor to AGND.
2	AGND	power_in	Analog ground reference.
3	AIN0P	input	Positive differential analog input 0, accepts voltage range AGND − 1.3 V to AVDD.
4	AIN0N	input	Negative differential analog input 0, accepts voltage range AGND − 1.3 V to AVDD.
5	AIN1N	input	Negative differential analog input 1, accepts voltage range AGND − 1.3 V to AVDD.
6	AIN1P	input	Positive differential analog input 1, accepts voltage range AGND − 1.3 V to AVDD.
7	AIN2P	input	Positive differential analog input 2, accepts voltage range AGND − 1.3 V to AVDD.
8	AIN2N	input	Negative differential analog input 2, accepts voltage range AGND − 1.3 V to AVDD.
9	AIN3N	input	Negative differential analog input 3, accepts voltage range AGND − 1.3 V to AVDD.
10	AIN3P	input	Positive differential analog input 3, accepts voltage range AGND − 1.3 V to AVDD.
11	SYNC/RESET	input	Active-low digital input for synchronization (pulse 1-2047 tCLKIN) or device reset (pulse ≥2048 tCLKIN).
12	CS	input	Chip select, active-low digital input for SPI slave selection.
13	DRDY	output	Data ready, active-low digital output indicating new ADC conversion data available.
14	SCLK	input	Serial clock digital input for SPI interface with 40-64 ns period.
15	DOUT	output	Serial data output for SPI interface, transitions on SCLK rising edges when CS is low.
16	DIN	input	Serial data input for SPI interface, latches commands and register data on SCLK falling edges when CS is low.
17	CLKIN	input	Master clock input, 0.3-8.192 MHz for high-resolution mode, must toggle continuously during normal operation.
18	CAP	power_out	Digital LDO regulator output for internal 1.8 V core voltage, requires 220-nF bypass capacitor to DGND.
19	DGND	power_in	Digital ground reference.
20	DVDD	power_in	Digital supply voltage, 2.7 V to 3.6 V (or 1.65-2 V if CAP tied to DVDD), requires 1-µF bypass capacitor to DGND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Data Acquisition
Pins	20

CAD (KiCad official)

Symbol: ADS131M04IPWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: ads131m04ipwr-etched.step / ads131m04ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads131m04ipwr.step / ads131m04ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (105 pp, sha256 cc5bfca62f8b1b0d, retrieved 2026-09-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF