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ADS131E08SPAGR

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Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS131E08SPAGR

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS131E08SPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Negative analog input 8; connect to AVDD if the input is unused or powered down.
2 IN8P input Positive analog input 8; connect to AVDD if the input is unused or powered down.
3 IN7N input Negative analog input 7; connect to AVDD if the input is unused or powered down.
4 IN7P input Positive analog input 7; connect to AVDD if the input is unused or powered down.
5 IN6N input Negative analog input 6; connect to AVDD if the input is unused or powered down.
6 IN6P input Positive analog input 6; connect to AVDD if the input is unused or powered down.
7 IN5N input Negative analog input 5; connect to AVDD if the input is unused or powered down.
8 IN5P input Positive analog input 5; connect to AVDD if the input is unused or powered down.
9 IN4N input Negative analog input 4; connect to AVDD if the input is unused or powered down.
10 IN4P input Positive analog input 4; connect to AVDD if the input is unused or powered down.
11 IN3N input Negative analog input 3; connect to AVDD if the input is unused or powered down.
12 IN3P input Positive analog input 3; connect to AVDD if the input is unused or powered down.
13 IN2N input Negative analog input 2; connect to AVDD if the input is unused or powered down.
14 IN2P input Positive analog input 2; connect to AVDD if the input is unused or powered down.
15 IN1N input Negative analog input 1; connect to AVDD if the input is unused or powered down.
16 IN1P input Positive analog input 1; connect to AVDD if the input is unused or powered down.
17 TESTP bidirectional Test signal, positive pin; connect to DGND with a 10-kΩ resistor if unused.
18 TESTN bidirectional Test signal, negative pin; connect to DGND with a 10-kΩ resistor if unused.
19 AVDD power_in Analog supply; decouple each AVDD pin to AVSS with a 1-µF capacitor.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog supply; decouple each AVDD pin to AVSS with a 1-µF capacitor.
22 AVDD power_in Analog supply; decouple each AVDD pin to AVSS with a 1-µF capacitor.
23 AVSS power_in Analog ground.
24 VREFP output Positive reference voltage output; connect a 330-nF capacitor to VREFN.
25 VREFN input Negative reference voltage; connect to AVSS.
26 VCAP4 output Analog bypass capacitor; connect a 270-nF capacitor to AVSS.
27 NC unconnected No connection, leave floating; can be connected to AVDD or AVSS with a 10-kΩ or higher resistor.
28 VCAP1 output Analog bypass capacitor; connect a 470-pF capacitor to AVSS.
29 NC unconnected No connection, leave floating; can be connected to AVDD or AVSS with a 10-kΩ or higher resistor.
30 VCAP2 output Analog bypass capacitor; connect a 270-nF capacitor to AVSS.
31 RESV1 input Reserved for future use; must tie to logic low by connecting to DGND.
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input SPI data input.
35 PWDN input Power-down; active low.
36 RESET input System reset; active low.
37 CLK input Master clock input; connect to DGND if unused.
38 START input Start conversion.
39 CS input Serial peripheral interface (SPI) chip select; active low.
40 SCLK input SPI clock.
41 DAISY_IN input Daisy-chain input; connect to DGND if unused.
42 GPIO1 bidirectional General-purpose input/output pin 1; connect to DGND with a 10-kΩ resistor if unused.
43 DOUT output SPI data output.
44 GPIO2 bidirectional General-purpose input/output pin 2; connect to DGND with a 10-kΩ resistor if unused.
45 GPIO3 bidirectional General-purpose input/output pin 3; connect to DGND with a 10-kΩ resistor if unused.
46 GPIO4 bidirectional General-purpose input/output pin 4; connect to DGND with a 10-kΩ resistor if unused.
47 DRDY output Data ready; active low; connect to DGND with a 10-kΩ resistor if unused.
48 DVDD power_in Digital power supply; decouple each DVDD pin to DGND with a 1-µF capacitor.
49 DGND power_in Digital ground.
50 DVDD power_in Digital power supply; decouple each DVDD pin to DGND with a 1-µF capacitor.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select.
53 AVSS1 power_in Charge pump analog ground; decouple AVDD1 to AVSS1 with a 1-µF capacitor.
54 AVDD1 power_in Charge pump analog supply; decouple AVDD1 to AVSS1 with a 1-µF capacitor.
55 VCAP3 output Analog bypass capacitor; connect a 270-nF capacitor to AVSS.
56 AVDD power_in Analog supply; decouple each AVDD pin to AVSS with a 1-µF capacitor.
57 AVSS power_in Analog ground.
58 AVSS power_in Analog ground.
59 AVDD power_in Analog supply; decouple each AVDD pin to AVSS with a 1-µF capacitor.
60 OPAMPP input Op amp noninverting input; leave floating if unused and power-down the op amp.
61 OPAMPN input Op amp inverting input; leave floating if unused and power-down the op amp.
62 NC unconnected No connection, leave floating; can be connected to AVDD or AVSS with a 10-kΩ or higher resistor.
63 OPAMPOUT output Op amp output; leave floating if unused and power-down the op amp.
64 NC unconnected No connection, leave floating; can be connected to AVDD or AVSS with a 10-kΩ or higher resistor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS131E08SPAGR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads131e08spagr-etched.step / ads131e08spagr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads131e08spagr.step / ads131e08spagr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (69 pp, sha256 7097eac06ddb802b, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF