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ADS1299-4PAG

Texas Instruments · Analog Front End (AFEs) · TQFP-64(10x10)

ADS1299-4PAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Differential analog negative input 8 (ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
2 IN8P input Differential analog positive input 8 (ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
3 IN7N input Differential analog negative input 7 (ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
4 IN7P input Differential analog positive input 7 (ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
5 IN6N input Differential analog negative input 6 (ADS1299-6 and ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
6 IN6P input Differential analog positive input 6 (ADS1299-6 and ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
7 IN5N input Differential analog negative input 5 (ADS1299-6 and ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
8 IN5P input Differential analog positive input 5 (ADS1299-6 and ADS1299 only); connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
9 IN4N input Differential analog negative input 4; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
10 IN4P input Differential analog positive input 4; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
11 IN3N input Differential analog negative input 3; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
12 IN3P input Differential analog positive input 3; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
13 IN2N input Differential analog negative input 2; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
14 IN2P input Differential analog positive input 2; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
15 IN1N input Differential analog negative input 1; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
16 IN1P input Differential analog positive input 1; connect unused analog inputs directly to AVDD and limit input current to 10 mA if the input exceeds the supply rails.
17 SRB1 bidirectional Patient stimulus, reference, and bias signal 1, used to route a common signal to multiple inputs in referential montages.
18 SRB2 bidirectional Patient stimulus, reference, and bias signal 2, used to route a common signal to multiple inputs in referential montages.
19 AVDD power_in Analog supply, connect a 1-μF capacitor to AVSS; analog supply range is 4.75 V to 5.25 V.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog supply, connect a 1-μF capacitor to AVSS; analog supply range is 4.75 V to 5.25 V.
22 AVDD power_in Analog supply, connect a 1-μF capacitor to AVSS; analog supply range is 4.75 V to 5.25 V.
23 AVSS power_in Analog ground.
24 VREFP bidirectional Positive analog reference voltage; connect a minimum 10-μF capacitor to VREFN.
25 VREFN input Negative analog reference voltage.
26 VCAP4 output Analog bypass capacitor pin; connect a 1-μF capacitor to AVSS.
27 NC unconnected No connection; leave as open circuit.
28 VCAP1 output Analog bypass capacitor pin; connect a 100-μF capacitor to AVSS.
29 NC unconnected No connection; leave as open circuit.
30 VCAP2 output Analog bypass capacitor pin; connect a 1-μF capacitor to AVSS.
31 RESV1 input Reserved for future use; connect directly to DGND.
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input Serial data input.
35 PWDN input Power-down, active low; pulling low powers down all on-chip circuitry.
36 RESET input System reset, active low.
37 CLK input Master clock input.
38 START input Synchronization signal to start or restart a conversion.
39 CS input Chip select, active low.
40 SCLK input Serial clock input.
41 DAISY_IN input Daisy-chain input.
42 GPIO1 bidirectional General-purpose input/output pin 1; connect to DGND with a ≥10-kΩ resistor if unused.
43 DOUT output Serial data output.
44 GPIO2 bidirectional General-purpose input/output pin 2; connect to DGND with a ≥10-kΩ resistor if unused.
45 GPIO3 bidirectional General-purpose input/output pin 3; connect to DGND with a ≥10-kΩ resistor if unused.
46 GPIO4 bidirectional General-purpose input/output pin 4; connect to DGND with a ≥10-kΩ resistor if unused.
47 DRDY output Data ready, active low.
48 DVDD power_in Digital power supply, connect a 1-μF capacitor to DGND; digital supply range is 1.8 V to 3.6 V.
49 DGND power_in Digital ground.
50 DVDD power_in Digital power supply, connect a 1-μF capacitor to DGND; digital supply range is 1.8 V to 3.6 V.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select; set high to DVDD or low to DGND through a ≥10-kΩ resistor.
53 AVSS1 power_in Analog ground.
54 AVDD1 power_in Analog supply, connect a 1-μF capacitor to AVSS1.
55 VCAP3 output Analog bypass capacitor pin; connect a parallel combination of 1-μF and 0.1-μF capacitors to AVSS.
56 AVDD power_in Analog supply, connect a 1-μF capacitor to AVSS; analog supply range is 4.75 V to 5.25 V.
57 AVSS power_in Analog ground.
58 AVSS power_in Analog ground for the charge pump.
59 AVDD power_in Charge pump analog supply, connect a 1-μF capacitor to AVSS (pin 58).
60 BIASREF input Bias drive noninverting input.
61 BIASINV bidirectional Bias drive inverting input.
62 BIASIN input Bias drive input to the input MUX.
63 BIASOUT output Bias drive output.
64 RESERVED output Reserved for future use; leave as open circuit.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category ADC/DAC/Data Conversion
Pins 64

CAD (KiCad official)

  • Symbol: ADS1299-4PAG
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads1299-4pag-etched.step / ads1299-4pag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1299-4pag.step / ads1299-4pag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (84 pp, sha256 9ef667389897f02d, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF