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ADS1298IPAG

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Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS1298IPAG

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1298IPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Differential analog negative input 8 for ADS1298 channels, 10 MΩ input impedance in normal mode.
2 IN8P input Differential analog positive input 8 for ADS1298 channels, 10 MΩ input impedance in normal mode.
3 IN7N input Differential analog negative input 7 for ADS1298 channels, 10 MΩ input impedance in normal mode.
4 IN7P input Differential analog positive input 7 for ADS1298 channels, 10 MΩ input impedance in normal mode.
5 IN6N input Differential analog negative input 6 for ADS1296/ADS1298 channels, 10 MΩ input impedance in normal mode.
6 IN6P input Differential analog positive input 6 for ADS1296/ADS1298 channels, 10 MΩ input impedance in normal mode.
7 IN5N input Differential analog negative input 5 for ADS1296/ADS1298 channels, 10 MΩ input impedance in normal mode.
8 IN5P input Differential analog positive input 5 for ADS1296/ADS1298 channels, 10 MΩ input impedance in normal mode.
9 IN4N input Differential analog negative input 4 for all channel configurations, 10 MΩ input impedance in normal mode.
10 IN4P input Differential analog positive input 4 for all channel configurations, 10 MΩ input impedance in normal mode.
11 IN3N input Differential analog negative input 3 for all channel configurations, 10 MΩ input impedance in normal mode.
12 IN3P input Differential analog positive input 3 for all channel configurations, 10 MΩ input impedance in normal mode.
13 IN2N input Differential analog negative input 2 for all channel configurations, 10 MΩ input impedance in normal mode.
14 IN2P input Differential analog positive input 2 for all channel configurations, 10 MΩ input impedance in normal mode.
15 IN1N input Differential analog negative input 1 for all channel configurations, 10 MΩ input impedance in normal mode.
16 IN1P input Differential analog positive input 1 for all channel configurations, 10 MΩ input impedance in normal mode.
17 TESTP_PACE_OUT1 bidirectional Internal test signal input or single-ended buffered output for PGA1/3/5/7 based on register configuration.
18 TESTN_PACE_OUT2 bidirectional Internal test signal input or single-ended buffered output for PGA2/4/6/8 based on register configuration.
19 AVDD power_in Analog power supply, 2.7 V to 5.25 V relative to AVSS.
20 AVSS power_in Analog ground reference for the device.
21 AVDD power_in Analog power supply, 2.7 V to 5.25 V relative to AVSS.
22 AVDD power_in Analog power supply, 2.7 V to 5.25 V relative to AVSS.
23 AVSS power_in Analog ground reference for the device.
24 VREFP bidirectional Positive reference input/output voltage; connect to VREFP pin if using external reference or internal bandgap output.
25 VREFN input Negative reference voltage input; typically connected to AVSS for internal reference mode.
26 VCAP4 passive Analog bypass capacitor node; connect 1 μF capacitor to AVSS.
27 NC unconnected No connect pin; may be connected to AVDD or AVSS through 10 kΩ resistor.
28 VCAP1 passive Analog bypass capacitor node; connect 22 μF capacitor to AVSS.
29 NC unconnected No connect pin; may be connected to AVDD or AVSS through 10 kΩ resistor.
30 VCAP2 passive Analog bypass capacitor node; connect 1 μF capacitor to AVSS.
31 RESV1 input Reserved for future use; must be connected to logic low (DGND).
32 AVSS power_in Analog ground reference for the device.
33 DGND power_in Digital ground reference for the device.
34 DIN input SPI serial data input; data is latched on falling edge of SCLK.
35 PWDN input Power down pin active low; all on-chip circuits power down when pulled low except reference.
36 RESET input System reset pin active low; resets registers to default values, requires 2 tCLK minimum pulse width.
37 CLK tri_state External master clock input when CLKSEL=0 or internal clock output when CLKSEL=1 and CLK_EN=1; typical 2.048 MHz.
38 START input Start conversion signal; pulling high for minimum 2 tCLK enables continuous or single-shot conversion.
39 CS input SPI chip select active low; selects device for serial communication when low.
40 SCLK input SPI serial clock; data is shifted on rising edge for output and latched on falling edge for input.
41 DAISY_IN input Daisy chain input for cascading multiple devices; must be connected to DGND if not used.
42 GPIO1 bidirectional General-purpose input/output pin 1; configurable as input or output via GPIO control register.
43 DOUT output SPI serial data output; data is shifted out on rising edge of SCLK and enters high-Z when CS is high.
44 GPIO2 bidirectional General-purpose input/output pin 2; configurable as input or output via GPIO control register.
45 GPIO3 bidirectional General-purpose input/output pin 3; configurable as input or output via GPIO control register.
46 GPIO4 bidirectional General-purpose input/output pin 4; configurable as input or output via GPIO control register.
47 DRDY output Data ready output active low; indicates when new conversion data is ready for reading.
48 DVDD power_in Digital power supply, 1.65 V to 3.6 V relative to DGND.
49 DGND power_in Digital ground reference for the device.
50 DVDD power_in Digital power supply, 1.65 V to 3.6 V relative to DGND.
51 DGND power_in Digital ground reference for the device.
52 CLKSEL input Master clock selection; logic low selects external clock on CLK pin, logic high selects internal oscillator.
53 AVSS1 power_in Charge pump analog ground; must be connected to AVSS.
54 AVDD1 power_in Charge pump analog power supply; powers internal charge pump circuit.
55 VCAP3 passive Analog bypass capacitor for internally generated AVDD + 1.9 V; connect 1 μF capacitor to AVSS.
56 AVDD power_in Analog power supply, 2.7 V to 5.25 V relative to AVSS.
57 AVSS power_in Analog ground reference for the device.
58 AVSS power_in Analog ground reference for the device.
59 AVDD power_in Analog power supply, 2.7 V to 5.25 V relative to AVSS.
60 RLDREF input Right leg drive amplifier non-inverting input; typically connected to (AVDD + AVSS)/2 or external reference.
61 RLDINV bidirectional Right leg drive amplifier inverting input; used for RLD feedback loop implementation.
62 RLDIN input Right leg drive input from multiplexer; can be routed to any electrode or used for RLD measurement.
63 RLDOUT output Right leg drive amplifier output; drives patient reference signal with typical ±0.25 mA short circuit current.
64 WCT output Wilson center terminal output; buffered average of selected electrodes (IN1-IN4) for 12-lead ECG reference.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS1298IPAG
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads1298ipag-etched.step / ads1298ipag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1298ipag.step / ads1298ipag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (113 pp, sha256 a8830f56bfd11d1b, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF