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ADS1296IPAGR

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Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS1296IPAGR

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1296IPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Differential analog negative input 8, used only on ADS1298; connect the pin to AVDD when unused.
2 IN8P input Differential analog positive input 8, used only on ADS1298; connect the pin to AVDD when unused.
3 IN7N input Differential analog negative input 7, used only on ADS1298; connect the pin to AVDD when unused.
4 IN7P input Differential analog positive input 7, used only on ADS1298; connect the pin to AVDD when unused.
5 IN6N input Differential analog negative input 6, used on ADS1296 and ADS1298; connect the pin to AVDD when unused.
6 IN6P input Differential analog positive input 6, used on ADS1296 and ADS1298; connect the pin to AVDD when unused.
7 IN5N input Differential analog negative input 5, used on ADS1296 and ADS1298; connect the pin to AVDD when unused.
8 IN5P input Differential analog positive input 5, used on ADS1296 and ADS1298; connect the pin to AVDD when unused.
9 IN4N input Differential analog negative input 4.
10 IN4P input Differential analog positive input 4.
11 IN3N input Differential analog negative input 3.
12 IN3P input Differential analog positive input 3.
13 IN2N input Differential analog negative input 2.
14 IN2P input Differential analog positive input 2.
15 IN1N input Differential analog negative input 1.
16 IN1P input Differential analog positive input 1.
17 TESTP_PACE_OUT1 bidirectional Internal test signal or single-ended buffered pace output, set by register; when pace detection is unused it can serve as an extra multiplexed differential input.
18 TESTN_PACE_OUT2 bidirectional Internal test signal or single-ended buffered pace output, set by register; when pace detection is unused it can serve as an extra multiplexed differential input.
19 AVDD power_in Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
22 AVDD power_in Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
23 AVSS power_in Analog ground.
24 VREFP bidirectional Positive reference input or output; VREF = VREFP minus VREFN is 2.5 V with a 3 V supply or 4 V with a 5 V supply.
25 VREFN input Negative reference voltage; connect to AVSS when the internal reference is used.
26 VCAP4 passive Analog bypass capacitor node; connect a 1 µF capacitor to AVSS.
27 NC unconnected No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor.
28 VCAP1 passive Analog bypass capacitor node; connect a 22 µF capacitor to AVSS.
29 NC unconnected No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor.
30 VCAP2 passive Analog bypass capacitor node; connect a 1 µF capacitor to AVSS.
31 RESV1 input Reserved for future use; must be connected to logic low (DGND).
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input SPI data input; latched on the falling edge of SCLK.
35 PWDN input Power-down pin, active low; pulling it low powers down all on-chip circuits.
36 RESET input System reset pin, active low; it must be held low for at least the minimum pulse width (2 tCLK).
37 CLK bidirectional External master clock input or internal clock output, depending on CLKSEL and CLK_EN.
38 START input Starts conversions when driven high for at least 2 tCLK (in pin-controlled mode), and stops them when low.
39 CS input SPI chip select, active low; it must stay low for the entire serial transfer.
40 SCLK input SPI serial clock input with Schmitt-trigger input; keep it clean to avoid spurious clock events.
41 DAISY_IN input Daisy-chain data input; tie to DGND when not used.
42 GPIO1 bidirectional General-purpose digital I/O 1; an input must be driven and not left floating, and the pin is tied to DGND when unused.
43 DOUT output SPI data output; data shifts out on the SCLK rising edge and the pin is high-impedance when CS is high.
44 GPIO2 bidirectional General-purpose digital I/O 2; an input must be driven and not left floating, and the pin is tied to DGND when unused.
45 GPIO3 bidirectional General-purpose digital I/O 3; an input must be driven and not left floating, and the pin is tied to DGND when unused.
46 GPIO4 bidirectional General-purpose digital I/O 4; an input must be driven and not left floating, and the pin is tied to DGND when unused.
47 DRDY output Data-ready output, active low; it goes low when new conversion data is available.
48 DVDD power_in Digital power supply; 1.65 V to 3.6 V.
49 DGND power_in Digital ground.
50 DVDD power_in Digital power supply; 1.65 V to 3.6 V.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select; low selects the external clock input (1.94 to 2.25 MHz), high selects the internal oscillator.
53 AVSS1 power_in Analog ground for the charge pump; connect in a star configuration to AVSS.
54 AVDD1 power_in Analog supply for the charge pump; connect in a star configuration to AVDD.
55 VCAP3 passive Internally generated AVDD + 1.9 V bypass node; connect a 1 µF capacitor to AVSS.
56 AVDD power_in Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
57 AVSS power_in Analog ground.
58 AVSS power_in Analog ground.
59 AVDD power_in Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
60 RLDREF input Right-leg drive non-inverting (reference) input.
61 RLDINV bidirectional Right-leg drive inverting input.
62 RLDIN input Multiplexer input for the right-leg drive signal.
63 RLDOUT output Right-leg drive output.
64 WCT output Wilson central terminal output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS1296IPAGR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads1296ipagr-etched.step / ads1296ipagr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1296ipagr.step / ads1296ipagr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (113 pp, sha256 a8830f56bfd11d1b, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF