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ADS1294IPAGR

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Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS1294IPAGR

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1294IPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Differential analog negative input 8, used on ADS1298 only; connect unused pin to AVDD.
2 IN8P input Differential analog positive input 8, used on ADS1298 only; connect unused pin to AVDD.
3 IN7N input Differential analog negative input 7, used on ADS1298 only; connect unused pin to AVDD.
4 IN7P input Differential analog positive input 7, used on ADS1298 only; connect unused pin to AVDD.
5 IN6N input Differential analog negative input 6, used on ADS1296 and ADS1298; connect unused pin to AVDD.
6 IN6P input Differential analog positive input 6, used on ADS1296 and ADS1298; connect unused pin to AVDD.
7 IN5N input Differential analog negative input 5, used on ADS1296 and ADS1298; connect unused pin to AVDD.
8 IN5P input Differential analog positive input 5, used on ADS1296 and ADS1298; connect unused pin to AVDD.
9 IN4N input Differential analog negative input 4.
10 IN4P input Differential analog positive input 4.
11 IN3N input Differential analog negative input 3.
12 IN3P input Differential analog positive input 3.
13 IN2N input Differential analog negative input 2.
14 IN2P input Differential analog positive input 2.
15 IN1N input Differential analog negative input 1.
16 IN1P input Differential analog positive input 1.
17 TESTP_PACE_OUT1 bidirectional Internal test signal or single-ended buffer output based on register settings; connect unused pin to AVDD.
18 TESTN_PACE_OUT2 bidirectional Internal test signal or single-ended buffer output based on register settings; connect unused pin to AVDD.
19 AVDD power_in Analog supply; AVDD minus AVSS is 2.7 V to 5.25 V.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog supply; AVDD minus AVSS is 2.7 V to 5.25 V.
22 AVDD power_in Analog supply; AVDD minus AVSS is 2.7 V to 5.25 V.
23 AVSS power_in Analog ground.
24 VREFP bidirectional Positive reference input/output voltage; VREFP minus VREFN is 2.5 V (3-V supply) or 4 V (5-V supply).
25 VREFN input Negative reference voltage input, referenced to AVSS.
26 VCAP4 passive Analog bypass capacitor; connect 1-μF capacitor to AVSS.
27 NC unconnected No connection; can be connected to AVDD or AVSS with a 10-kΩ resistor.
28 VCAP1 passive Analog bypass capacitor; connect 22-μF capacitor to AVSS.
29 NC unconnected No connection; can be connected to AVDD or AVSS with a 10-kΩ resistor.
30 VCAP2 passive Analog bypass capacitor; connect 1-μF capacitor to AVSS.
31 RESV1 input Reserved for future use; must tie to logic low (DGND).
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input SPI data input.
35 PWDN input Power-down pin; active low.
36 RESET input System-reset pin; active low.
37 CLK bidirectional External master clock input or internal clock output; external clock frequency is 1.94 to 2.25 MHz when CLKSEL = 0.
38 START input Start conversion.
39 CS input SPI chip select; active low.
40 SCLK input SPI clock input.
41 DAISY_IN input Daisy-chain input; when not used, tie to logic 0.
42 GPIO1 bidirectional General-purpose input/output pin 1.
43 DOUT output SPI data output.
44 GPIO2 bidirectional General-purpose input/output pin 2.
45 GPIO3 bidirectional General-purpose input/output pin 3.
46 GPIO4 bidirectional General-purpose input/output pin 4.
47 DRDY output Data ready; active low.
48 DVDD power_in Digital power supply; 1.65 V to 3.6 V.
49 DGND power_in Digital ground.
50 DVDD power_in Digital power supply; 1.65 V to 3.6 V.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select.
53 AVSS1 power_in Analog ground for the charge pump.
54 AVDD1 power_in Analog supply for the charge pump.
55 VCAP3 passive Internally generated AVDD + 1.9 V bypass; connect 1-μF capacitor to AVSS.
56 AVDD power_in Analog supply; AVDD minus AVSS is 2.7 V to 5.25 V.
57 AVSS power_in Analog ground.
58 AVSS power_in Analog ground.
59 AVDD power_in Analog supply; AVDD minus AVSS is 2.7 V to 5.25 V.
60 RLDREF input Right leg drive noninverting input.
61 RLDINV bidirectional Right leg drive inverting input.
62 RLDIN input Right leg drive input to mux; connect unused pin to AVDD.
63 RLDOUT output Right leg drive output.
64 WCT output Wilson Central Terminal output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog power supply (AVDD - AVSS) 2.7 3 5.25 V 12
Digital power supply DVDD 1.65 1.8 3.6 V 12
AVDD - DVDD -2.1 3.6 V 12
External clock input frequency fCLK 1.94 2.048 2.25 MHz CLKSEL pin = 0 12
Operating temperature range (industrial grade) -40 85 °C Industrial grade 12
AVDD to AVSS -0.3 5.5 V 12
DVDD to DGND -0.3 3.9 V 12
AVSS to DGND -3 0.2 V 12
Input current (momentary) 100 mA 12
Input current (continuous) 10 mA 12
Junction temperature TJ -40 150 °C 12
Storage temperature Tstg -60 150 °C 12
Input bias current -200 200 pA TA = 25°C, input = 1.5 V 13
Input bias current -1.2 1.2 nA TA = -40°C to +85°C, input = 1.5 V 13
Offset error -500 500 µV 13
Gain error -0.5 0.5 % of FS Excluding voltage reference error 13
Input-referred noise 4 7 µVPP Gain = 6, 256 points, 0.5 seconds of data 13
Data rate (HR mode) 500 32000 SPS fCLK = 2.048 MHz, HR mode 13
Data rate (LP mode) 250 16000 SPS fCLK = 2.048 MHz, LP mode 13
Common-mode rejection ratio CMRR -105 -115 dB fCM = 50 Hz, 60 Hz 14
Power-supply rejection ratio PSRR 90 dB fPS = 50 Hz, 60 Hz 14
Signal-to-noise ratio SNR 112 dB fIN = 10 Hz input, gain = 6 14
Power dissipation (ADS1294, HR mode) 5.4 6 mW AVDD - AVSS = 3 V, HR mode 16
Power dissipation (ADS1294, LP mode 250 SPS) 4.1 4.4 mW AVDD - AVSS = 3 V, LP mode (250 SPS) 16
Digital input voltage, low-level output VOL 0.4 V IOL = 500 µA 16
Input current (digital input) IIN -10 10 µA 0 V < VDigitalInput < DVDD 16
VREF accuracy -0.2 0.2 % 15
Internal reference drift 45 ppm Industrial grade, -40°C to 85°C 15
Internal clock accuracy -0.5 0.5 % TA = 25°C 15
Internal clock accuracy -2.5 2.5 % -40°C ≤ TA ≤ 85°C, industrial grade versions only 15
Test-signal accuracy -2 2 % 15
Master clock period (tCLK) tCLK 414 514 ns 2.7 V ≤ DVDD ≤ 3.6 V 17
Junction-to-ambient thermal resistance RθJA 35 °C/W PAG (TQFP), 64 pins 13
Junction-to-case (top) thermal resistance RθJC(top) 31 °C/W PAG (TQFP), 64 pins 13
Junction-to-board thermal resistance RθJB 26 °C/W PAG (TQFP), 64 pins 13
Junction-to-top characterization parameter ψJT 0.1 °C/W PAG (TQFP), 64 pins 13

CAD (KiCad official)

  • Symbol: ADS1294IPAGR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads1294ipagr-etched.step / ads1294ipagr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1294ipagr.step / ads1294ipagr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (113 pp, sha256 412193168ffdaf64, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF