# ADS1283BIRHFR

**Texas Instruments** · Analog To Digital Converters (ADCs) · VQFN-24-EP(4x5)

ADS1283BIRHFR from Texas Instruments, in a VQFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRDY | output | Data ready output, active low, signals that a conversion result is available. |
| 2 | DOUT | output | Serial interface data output. |
| 3 | DIN | input | Serial interface data input. |
| 4 | CS | input | Serial interface chip select, active low. |
| 5 | SYNC | input | Synchronize input, active on the rising edge, used to synchronize conversions across multiple ADS1283 devices. |
| 6 | MFLAG | output | Modulator overrange flag: 0 = normal, 1 = modulator overrange. |
| 7 | DGND | power_in | Digital ground, to be tied to the digital ground plane. |
| 8 | CAPN | output | PGA output; connect a 10-nF capacitor from CAPP to CAPN. |
| 9 | CAPP | output | PGA output; connect a 10-nF capacitor from CAPP to CAPN. |
| 10 | AINP2 | input | Positive analog input 2. |
| 11 | AINN2 | input | Negative analog input 2. |
| 12 | AINP1 | input | Positive analog input 1. |
| 13 | AINN1 | input | Negative analog input 1. |
| 14 | AVDD | power_in | Positive analog power supply; AVDD must be AVSS + 4.75 V to AVSS + 5.25 V (recommended operating conditions). |
| 15 | AVSS | power_in | Negative analog power supply, -2.6 V to 0 V relative to DGND per recommended operating conditions. |
| 16 | VREFN | input | Negative reference input; AVSS - 0.1 V to VREFP - 1 V per recommended operating conditions. |
| 17 | VREFP | input | Positive reference input; VREFN + 1 V to AVDD + 0.1 V per recommended operating conditions. |
| 18 | PWDN | input | Power-down input, active low. |
| 19 | RESET | input | Reset input, active low. |
| 20 | DVDD | power_in | Digital power supply, 1.65 V to 3.6 V. |
| 21 | DGND | power_in | Digital ground, to be tied to the digital ground plane. |
| 22 | BYPAS | output | 1.8-V sub-regulator output; connect a 1-µF capacitor to DGND. |
| 23 | CLK | input | Master clock input, 4.096 MHz. |
| 24 | SCLK | input | Serial interface shift clock input. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x5) |
| Category | ADC/DAC/Data Conversion |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Negative analog supply AVSS (relative to DGND) | AVSS | -2.6 |  | 0 | V | relative to DGND | 5 |
| Positive digital supply DVDD (relative to DGND) | DVDD | 1.65 |  | 3.6 | V | relative to DGND | 5 |
| Clock input | fCLK | 1 |  | 4.096 | MHz |  | 5 |
| Specified temperature |  | -40 |  | 85 | °C |  | 5 |
| Reference input voltage | VREF | 1 | 5 |  | V | VREF = VREFP, VREFN | 5 |
| AVDD to AVSS |  | -0.3 |  | 5.5 | V |  | 5 |
| AVSS to DGND |  | -2.8 |  | 0.3 | V |  | 5 |
| DVDD to DGND |  | -0.3 |  | 3.9 | V |  | 5 |
| Input current, continuous |  | -10 |  | 10 | mA |  | 5 |
| Operating temperature |  | -50 |  | 125 | °C | over operating free-air temperature range | 5 |
| Junction temperature |  |  |  | 150 | °C |  | 5 |
| Storage temperature | Tstg | -60 |  | 150 | °C |  | 5 |
| Output impedance tolerance (PGA output) |  | -10 |  | 10 | % |  | 6 |
| External bypass capacitance (CAPP, CAPN) |  | 10 |  | 100 | nF |  | 6 |
| Signal-to-noise ratio | SNR | 120 | 124 |  | dB | Inputs shorted (footnote 2) | 6 |
| Total harmonic distortion, ADS1283 and ADS1283B, PGA = 1, 2, 4, 8, 16 | THD |  | -122 | -114 | dB | Input 31.25 Hz, -0.5 dBFS (footnote 3) | 6 |
| Total harmonic distortion, ADS1283 and ADS1283B, PGA = 32 | THD |  | -117 | -110 | dB | Input 31.25 Hz, -0.5 dBFS (footnote 3) | 6 |
| Data rate, FIR filter mode | fDATA | 250 |  | 4000 | SPS | FIR filter mode | 7 |
| Data rate, sinc filter mode | fDATA | 8000 |  | 128000 | SPS | Sinc filter mode | 7 |
| Offset (input referred), OFFSET disabled |  | -200 | 50 | 200 | µV | OFFSET disabled | 7 |
| Gain error |  | -1.5 | -1 | -0.5 | % |  | 7 |
| Gain matching |  |  | 0.3 | 0.8 | % | Relative to gain = 1 (footnote 7) | 7 |
| Common-mode rejection | CMR | 95 | 110 |  | dB | fCM = 60 Hz, 1.25 VPP (footnote 8) | 7 |
| Power-supply rejection, AVDD, AVSS | PSR | 80 | 90 |  | dB | fPS = 60 Hz, 100 mVPP (footnote 8) | 7 |
| Power-supply rejection, DVDD | PSR | 90 | 115 |  | dB | fPS = 60 Hz, 100 mVPP (footnote 8) | 7 |
| High-pass filter corner |  | 0.1 |  | 10 | Hz |  | 7 |
| Pass-band ripple |  | -0.003 |  | 0.003 | dB |  | 7 |
| Input leakage | Ilkg | -10 |  | 10 | µA | 0 < VDIGITAL IN < DVDD | 8 |
| AVDD, AVSS current, operating |  |  | 3.2 | 5.5 | mA | PGA = 1, 2, 4, 8 | 8 |
| AVDD, AVSS current, operating |  |  | 4 | 6 | mA | PGA = 16, 32, 64 | 8 |
| AVDD, AVSS current, standby mode |  |  | 1 | 15 | µA | Standby mode | 8 |
| AVDD, AVSS current, power-down mode |  |  | 1 | 15 | µA | Power-down mode | 8 |
| DVDD current, operating |  |  | 0.6 | 0.8 | mA |  | 8 |
| DVDD current, standby mode |  |  | 25 | 50 | µA | Standby mode | 8 |
| DVDD current, power-down mode |  |  | 1 | 15 | µA | Power-down mode (footnote 11): CLK input stopped | 8 |
| Power dissipation, operating |  |  | 18 | 30 | mW | PGA = 1, 2, 4, 8 | 8 |
| Power dissipation, operating |  |  | 22 | 33 | mW | PGA = 16, 32, 64 | 8 |
| Power dissipation, standby mode |  |  | 90 | 250 | µW | Standby mode | 8 |
| Power dissipation, power-down mode |  |  | 10 | 125 | µW | Power-down mode | 8 |
| CS low to SCLK high setup time | tCSSC | 40 |  |  | ns | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V | 9 |
| SCLK period | tSCLK | 2 |  | 16 | 1/fCLK | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V | 9 |
| SCLK pulse duration, high and low | tSPWH, L | 0.8 |  | 10 | 1/fCLK | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V (footnote 1) | 9 |
| DIN valid to SCLK high setup time | tDIST | 50 |  |  | ns | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V | 9 |
| Valid DIN to SCLK high hold time | tDIHD | 50 |  |  | ns | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V | 9 |
| CS high pulse | tCSH | 100 |  |  | ns | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V | 9 |
| SCLK high to CS high | tSCCS | 24 |  |  | 1/fCLK | TA = -40°C to +85°C; DVDD = 1.65 V to 3.6 V | 9 |
| CS low to DOUT driven, propagation delay | tCSDOD |  |  | 60 | ns |  | 9 |
| SCLK low to valid new DOUT, propagation delay | tDOPD |  |  | 100 | ns | Load on DOUT = 20 pF // 100 kΩ | 9 |
| SCLK low to DOUT invalid, hold time | tDOHD | 0 |  |  | ns |  | 9 |
| CS high to DOUT tristate | tCSDOZ |  |  | 40 | ns |  | 9 |
| Junction-to-ambient thermal resistance | RθJA |  | 30.2 |  | °C/W |  | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 27.5 |  | °C/W |  | 6 |
| Junction-to-board thermal resistance | RθJB |  | 8.5 |  | °C/W |  | 6 |
| Junction-to-top characterization parameter | ψJT |  | 0.3 |  | °C/W |  | 6 |
| Junction-to-board characterization parameter | ψJB |  | 8.6 |  | °C/W |  | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 1.7 |  | °C/W |  | 6 |

## CAD (KiCad official)

- Symbol: `ADS1283BIRHFR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm`
- 3D model: VQFN-24-EP(4x5) (KiCad packages3D, STEP)
- 3D model files: `ads1283birhfr-etched.step` / `ads1283birhfr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1283birhfr.step` / `ads1283birhfr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ads1283birhfr.pdf) (68 pp, sha256 `6e9fc54f7ea0b7c0`, retrieved 2026-10-30, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ads1283birhfr-datasheet.pdf)