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ADS1281IPWR

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Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS1281IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-24

ADS1281IPWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input Master clock input; the ADS1281 requires a clock input for operation and the data conversion rate scales directly with the CLK frequency.
2 SCLK input SPI serial clock input used to clock data on DIN and DOUT.
3 DRDY output Data ready output; read the data on its falling edge.
4 DOUT output SPI serial data output.
5 MOD/DIN input In register mode this is the SPI serial data input (DIN); in pin mode it is the MOD input that selects the modulator mode (0 = digital filter mode, 1 = filter bypass, modulator output).
6 DGND power_in Digital ground.
7 PHS/MCLK bidirectional In pin mode with MOD = 0 it is the PHS input selecting linear phase (0) or minimum phase (1) filter; with MOD = 1, or in register mode, it is the MCLK modulator clock output.
8 DR1/M1 bidirectional In pin mode with MOD = 0 it is the DR1 data rate select input; with MOD = 1, or in register mode, it is the M1 modulator data output 1.
9 DR0/M0 bidirectional In pin mode with MOD = 0 it is the DR0 data rate select input; with MOD = 1, or in register mode, it is the M0 modulator data output 0.
10 HPF/SYNC input In pin mode it is the HPF input (0 = high-pass filter off, 1 = HPF on); in register mode it is the SYNC input.
11 MFLAG output Modulator over-range flag: 0 = normal, 1 = modulator over-range.
12 DGND power_in Digital ground; pin 12 is the key ground point.
13 AINP input Positive analog input; the input must stay within AVSS - 300 mV to AVDD + 300 mV to keep the ESD diodes off.
14 AINN input Negative analog input; the input must stay within AVSS - 300 mV to AVDD + 300 mV to keep the ESD diodes off.
15 AVDD power_in Positive analog power supply (AVDD - AVSS is specified at 4.75 V to 5.25 V).
16 AVSS power_in Negative analog power supply (AVSS is specified at -2.6 V to 0 V).
17 VREFN input Negative reference input; VREFN must be within AVSS - 0.1 V to VREFP - 0.5 V.
18 VREFP input Positive reference input; VREFP must be within VREFN + 0.5 V to AVDD + 0.1 V.
19 PWDN input Power-down input, active low.
20 RESET input Reset input in register mode; in pin mode this pin is the sync input.
21 PINMODE input Control mode select: 1 = pin mode, 0 = register mode.
22 DVDD power_in Digital power supply, +1.8 V to +3.3V (DVDD is specified at 1.65 V to 3.6 V in the electrical characteristics).
23 DGND power_in Digital ground.
24 BYPAS passive Digital core bypass; connect a 1mF bypass capacitor to GND as printed in the datasheet.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Data Acquisition
Pins 24

CAD (KiCad official)

  • Symbol: ADS1281IPWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ads1281ipwr-etched.step / ads1281ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1281ipwr.step / ads1281ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (51 pp, sha256 e7708c8998f267c1, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF