component
ADS127L21IRUKR
Public Made by Adomby adom
Texas Instruments Global Sourcing Parts, WQFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS127L21IRUKR
Texas Instruments · Global Sourcing Parts · WQFN-20-EP(3x3)
ADS127L21IRUKR from Texas Instruments, in a WQFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AINP | input | Positive differential analog input; the input is defined as VIN = VAINP - VAINN, with the common mode centred at (AVDD1 + AVSS)/2 for best performance. |
| 2 | AINN | input | Negative differential analog input; it can be tied to AVSS, ground or mid-supply for single-ended operation, which limits the input swing to the AINP range. |
| 3 | VCM | output | Common-mode voltage output at (AVDD1 + AVSS)/2 that biases the common-mode control input of an external fully differential amplifier; rated 10 mA short-circuit limit and 100 nF maximum capacitive load on page 13, and it can be left unconnected if unused. |
| 4 | REFP | input | Positive differential reference input; VREF = VREFP - VREFN, and the reference pins must not go more than 0.3 V below AVSS or 0.3 V above AVDD1. |
| 5 | REFN | input | Negative differential reference input; it must stay within AVSS - 0.05 V to the recommended limits, and it is typically tied to ground in many applications. |
| 6 | RESET | input | Active-low reset input with an internal 20 kΩ pull-up and a Schmitt-trigger input; pulling it low and then high resets the ADC. |
| 7 | CS | input | Active-low chip select that starts and ends an SPI frame; tying it low selects 3-wire SPI operation. |
| 8 | SDI | input | Serial data input to the device, latched on the falling edge of SCLK. |
| 9 | SCLK | input | Serial data clock input (Schmitt-trigger) that shifts data in and out; output data updates on its rising edge and input data is latched on its falling edge. |
| 10 | SDO/DRDY | output | Dual-function serial data output and data-ready output that can be programmed for data-only or combined data/data-ready operation; it is high impedance when CS is high. |
| 11 | DRDY | output | Active-low data-ready output that goes low when new conversion data is available and is driven high again during data readback. |
| 12 | CLK | input | Clock input for external-clock operation, with frequency limits of 0.5 MHz to 32.768 MHz depending on speed mode (recommended operating conditions, page 5). |
| 13 | IOVDD | power_in | Digital I/O supply, referenced to DGND, rated 1.65 V to 5.5 V; it also feeds the internal digital regulator (regulated to 1.35 V at CAPD). |
| 14 | DGND | power_in | Digital ground reference for IOVDD and the digital pins. |
| 15 | CAPD | passive | Digital regulator output (1.35 V typical, referenced to DGND) that must be bypassed with a 1 µF capacitor to DGND and is not intended to drive external loads. |
| 16 | START | input | Conversion start input that synchronises the digital filter and controls conversions depending on the selected start mode. |
| 17 | AVSS | power_in | Negative analog supply; in unipolar operation it is tied to DGND (0 V), and in bipolar operation it is set to a negative supply (for example -2.5 V), with AVSS to DGND limited to -2.75 V to 0 V. |
| 18 | CAPA | passive | Analog regulator output (1.6 V referenced to AVSS) that must be bypassed with a 1 µF capacitor to AVSS and is not intended to drive external loads. |
| 19 | AVDD2 | power_in | Positive analog supply referenced to AVSS that powers the modulator core, rated 1.74 V to 5.5 V (recommended operating conditions, page 5). |
| 20 | AVDD1 | power_in | Positive analog supply that powers the input and reference precharge buffers and sampling switches; the supply range is 2.85 V to 5.5 V depending on speed mode, with AVDD1 to DGND at 1.65 V minimum. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-20-EP(3x3) |
| Category | Global Sourcing Parts |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 模拟电源 AVDD1 至 AVSS（最大速度模式） | AVDD1 | 4.5 | 5.5 | V | 最大速度模式 | 5 | |
| 模拟电源 AVDD1 至 AVSS（高速模式） | AVDD1 | 4.5 | 5.5 | V | 高速模式 | 5 | |
| 模拟电源 AVDD1 至 AVSS（中速模式） | AVDD1 | 3 | 5.5 | V | 中速模式 | 5 | |
| 模拟电源 AVDD1 至 AVSS（低速模式） | AVDD1 | 2.85 | 5.5 | V | 低速模式 | 5 | |
| 模拟电源 AVDD2 至 AVSS | AVDD2 | 1.74 | 5.5 | V | 5 | ||
| AVSS 至 DGND | AVSS | -2.75 | 0 | V | 5 | ||
| 数字电源 IOVDD 至 DGND | IOVDD | 1.65 | 5.5 | V | 5 | ||
| 差分基准电压 低基准范围 | VREF | 0.5 | 2.5 | 2.75 | V | 低基准范围 | 5 |
| 差分基准电压 高基准范围 | VREF | 1 | 4.096 | V | 高基准范围；最大值表中印为 AVDD1, AVSS，未转换为数值 | 5 | |
| 时钟频率 fCLK（最大速度模式） | fCLK | 0.5 | 32.768 | 33.66 | MHz | 最大速度模式 | 5 |
| 时钟频率 fCLK（高速模式） | fCLK | 0.5 | 25.6 | 26.3 | MHz | 高速模式 | 5 |
| 时钟频率 fCLK（中速模式） | fCLK | 0.5 | 12.8 | 13.15 | MHz | 中速模式 | 5 |
| 时钟频率 fCLK（低速模式） | fCLK | 0.5 | 3.2 | 3.29 | MHz | 低速模式 | 5 |
| 环境温度 TA（工作中） | TA | -45 | 125 | °C | 工作中 | 5 | |
| 环境温度 TA（规格） | TA | -40 | 125 | °C | 规格 | 5 | |
| 模拟输入，最大速度模式：输入电流，差分输入电压 | -4 | 4 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，最大速度模式：输入电流，共模输入电压 | -4 | 4 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，高速模式：输入电流，差分输入电压 | -3 | 3 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，高速模式：输入电流，共模输入电压 | -3 | 3 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，中速模式：输入电流，差分输入电压 | -1.5 | 1.5 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，中速模式：输入电流，共模输入电压 | -1.5 | 1.5 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，低速模式：输入电流，差分输入电压 | -0.4 | 0.4 | µA | 预充电缓冲器开启 | 6 | ||
| 模拟输入，低速模式：输入电流，共模输入电压 | -0.4 | 0.4 | µA | 预充电缓冲器开启 | 6 | ||
| 偏移误差 | -250 | 250 | µV | TA = 25°C | 7 | ||
| 偏移漂移 | 50 | 200 | nV/°C | 7 | |||
| 增益误差 | -2500 | 2500 | FSR 的 ppm 值 | TA = 25°C | 7 | ||
| 增益漂移 | 0.5 | 1 | FSR/°C 的 ppm 值 | 7 | |||
| INL 积分非线性 | 0.4 | 1.4 | FSR 的 ppm 值 | TA = 25°C ± 5°C | 7 | ||
| INL 积分非线性 | 0.4 | 1.8 | FSR 的 ppm 值 | TA = 0°C 至 70°C | 7 | ||
| INL 积分非线性 | 0.4 | 2.2 | FSR 的 ppm 值 | TA = -40°C 至 125°C | 7 | ||
| INL 积分非线性 | 1.5 | 5 | FSR 的 ppm 值 | 最大速度模式 | 7 | ||
| 动态范围 DR（宽带滤波器，最大速度模式） | DR | 109 | 111.5 | dB | 输入短接，OSR = 64，fDATA = 256kSPS；宽带滤波器 | 7 | |
| REFP 输入电流 | -2 | 2 | µA | REFP 预充电缓冲器开启 | 13 | ||
| 内部振荡器频率 | 25.4 | 25.6 | 25.8 | MHz | 13 | ||
| VCM 输出电压精度 | -1 | 1 | % | 13 | |||
| 数字输入电流 | -1 | 1 | µA | 不包括 RESET 引脚 | 13 | ||
| IAVDD1、IAVSS AVDD1 和 AVSS 电流（缓冲器关闭） | IAVDD1 | 2.1 | 2.2 | mA | 最大速度模式 | 14 | |
| IAVDD1、IAVSS AVDD1 和 AVSS 电流（缓冲器关闭） | IAVDD1 | 1.7 | 1.8 | mA | 高速模式 | 14 | |
| IAVDD1、IAVSS AVDD1 和 AVSS 电流（缓冲器关闭） | IAVDD1 | 0.9 | 1 | mA | 中速模式 | 14 | |
| IAVDD1、IAVSS AVDD1 和 AVSS 电流（缓冲器关闭） | IAVDD1 | 0.25 | 0.3 | mA | 低速模式 | 14 | |
| IAVDD2、IAVSS AVDD2 和 AVSS 电流 | IAVDD2 | 4.5 | 4.9 | mA | 最大速度模式 | 14 | |
| IAVDD2、IAVSS AVDD2 和 AVSS 电流 | IAVDD2 | 3.5 | 3.8 | mA | 高速模式 | 14 | |
| IAVDD2、IAVSS AVDD2 和 AVSS 电流 | IAVDD2 | 2.2 | 2.5 | mA | 中速模式 | 14 | |
| IAVDD2、IAVSS AVDD2 和 AVSS 电流 | IAVDD2 | 0.85 | 0.95 | mA | 低速模式 | 14 | |
| IIOVDD IOVDD 电流（宽带滤波器，OSR = 32，IIR 滤波器关闭） | IIOVDD | 7.2 | 8.5 | mA | 最大速度模式 | 14 | |
| IIOVDD IOVDD 电流（宽带滤波器，OSR = 32，IIR 滤波器关闭） | IIOVDD | 5.7 | 6.8 | mA | 高速模式 | 14 | |
| IIOVDD IOVDD 电流（宽带滤波器，OSR = 32，IIR 滤波器关闭） | IIOVDD | 2.8 | 3.4 | mA | 中速模式 | 14 | |
| IIOVDD IOVDD 电流（宽带滤波器，OSR = 32，IIR 滤波器关闭） | IIOVDD | 0.75 | 0.9 | mA | 低速模式 | 14 | |
| 结至环境热阻 RθJA | RθJA | 58.3 | °C/W | 5 | |||
| 结至外壳（顶部）热阻 RθJC(top) | RθJC(top) | 39.9 | °C/W | 5 | |||
| 结至电路板热阻 RθJB | RθJB | 29.2 | °C/W | 5 | |||
| 结至顶部特征参数 ψJT | ψJT | 0.8 | °C/W | 5 | |||
| 结至电路板特征参数 ψJB | ψJB | 29.1 | °C/W | 5 | |||
| 结至外壳（底部）热阻 RθJC(bot) | RθJC(bot) | 25.9 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
ADS127L21IRUKR - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: WQFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ads127l21irukr-etched.step/ads127l21irukr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads127l21irukr.step/ads127l21irukr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (121 pp, sha256
95dc8cc6df030081, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).