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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS1271IPW

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-16

ADS1271IPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AINP	input	Positive analog input; the differential input is VIN = AINP − AINN, and AINP must stay within AGND − 0.3 V to AVDD + 0.3 V (absolute maximum).
2	AINN	input	Negative analog input forming the differential pair with AINP; it must stay within AGND − 0.3 V to AVDD + 0.3 V (absolute maximum).
3	AGND	power_in	Analog ground; AGND to DGND is limited to −0.3 V to +0.3 V (absolute maximum).
4	AVDD	power_in	Analog supply, specified at 4.75 V to 5.25 V (5 V nominal), with an absolute maximum of −0.3 V to +6.0 V to AGND.
5	MODE	input	Operating-mode select: MODE = 0 selects High-Speed mode, MODE = float selects High-Resolution mode, and MODE = 1 selects Low-Power mode.
6	FORMAT	input	Serial-interface select: FORMAT = 0 selects SPI, FORMAT = 1 selects Frame-Sync, and FORMAT = float selects modulator output, which the datasheet notes applies to the ADS1271B only.
7	SYNC/PDWN	input	Active-low synchronize and power-down input that is used to synchronize conversions or power down the device.
8	DIN	input	Data input for daisy-chain operation, shifted in on the falling edge of SCLK; tie DIN low when only one ADS1271 is used.
9	DOUT	output	ADC conversion data output, shifted out MSB first on the falling edge of SCLK, or the modulator data output in modulator mode.
10	DRDY/FSYNC	bidirectional	Acts as the DRDY output in SPI format, going low when data is ready, and as the FSYNC frame-sync input in Frame-Sync format.
11	SCLK	input	Serial clock for data retrieval with a Schmitt-triggered input that may run as fast as the CLK frequency, becoming the modulator clock output in modulator mode.
12	CLK	input	Master clock input, specified from 0.1 MHz to 27 MHz.
13	DVDD	power_in	Digital supply, specified at 1.65 V to 3.6 V with an absolute maximum of −0.3 V to +3.6 V to DGND.
14	DGND	power_in	Digital ground.
15	VREFN	input	Negative reference input, specified from AGND − 0.1 V to VREFP − 2.0 V for the ADS1271.
16	VREFP	input	Positive reference input, specified from VREFN + 2.0 V to AVDD − 0.5 V for the ADS1271.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Data Acquisition
Pins	16

CAD (KiCad official)

Symbol: ADS1271IPW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ads1271ipw-etched.step / ads1271ipw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1271ipw.step / ads1271ipw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 e557bad6e4152574, retrieved 2026-10-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF