component
ADS125H02IRHBR
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Texas Instruments Analog To Digital Converters (ADC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# ADS125H02IRHBR++**Texas Instruments** · Analog To Digital Converters (ADC) · VQFN-32-EP(5x5)++ADS125H02IRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | REFP0 | input | Reference 0 positive input; differential reference voltage 0.9 V to AVDD V relative to REFN0. |+| 2 | CAPP | output | PGA output positive; connect 1-nF C0G dielectric capacitor to CAPN for antialias filtering. |+| 3 | CAPN | output | PGA output negative; connect 1-nF C0G dielectric capacitor to CAPP for antialias filtering. |+| 4 | AVDD | power_in | Low-voltage analog power supply; nominal 5 V with operating range 4.75 V to 5.25 V. |+| 5 | AGND | power_in | Analog ground; connect to the ADC ground plane for signal and power return. |+| 6 | REFOUT | output | 2.5-V internal reference output; connect 10-µF capacitor to AGND for noise filtering. |+| 7 | RESET | input | Reset input active low; pulse low for minimum 4 fCLK cycles to reset device. |+| 8 | START | input | Conversion start input active high; triggers single or continuous conversion based on mode. |+| 9 | CS2 | input | Serial interface chip select 2 active low; selects PGA registers for SPI communication. |+| 10 | CS1 | input | Serial interface chip select 1 active low; selects ADC registers for SPI communication. |+| 11 | SCLK | input | Serial clock input; 97 ns minimum period required for SPI interface with 40-60% duty cycle. |+| 12 | DIN | input | Serial data input; latched on SCLK falling edge with 25 ns minimum setup time. |+| 13 | DRDY | output | Data-ready output active low; asserts when new conversion data are available for readback. |+| 14 | DOUT/DRDY | tri_state | Serial data output and data-ready indicator in tri-state; functions as data output during read or DRDY signal between operations. |+| 15 | BYPASS | output | 2-V subregulator output; connect 1-µF capacitor to DGND for digital core supply decoupling. |+| 16 | DGND | power_in | Digital ground; connect to the ADC ground plane for digital signal return. |+| 17 | DVDD | power_in | Digital power supply; operating range 2.7 V to 5.25 V for digital I/O and core regulator. |+| 18 | CLKIN | input | External clock input; connect to DGND for internal 7.3728 MHz oscillator operation. |+| 19 | HV_AVSS | power_in | High-voltage negative analog power supply; operating range -18 V to 0 V relative to HV_AVDD. |+| 20 | HV_AVDD | power_in | High-voltage positive analog power supply; operating range 5 V to 36 V for unipolar or ±5 V to ±18 V bipolar. |+| 21 | NC | unconnected | No connection; electrically float or tie to AGND per application requirements. |+| 22 | NC | unconnected | No connection; electrically float or tie to AGND per application requirements. |+| 23 | IDAC2 | output | Current source 2 output; provides 50 µA to 3000 µA programmable excitation current for sensor biasing. |+| 24 | IDAC1 | output | Current source 1 output; provides 50 µA to 3000 µA programmable excitation current for sensor biasing. |+| 25 | AINCOM | input | Analog input common for single-ended measurements; 1 GΩ minimum input impedance to reference. |+| 26 | AIN0 | input | Analog input 0; accepts ±20 V differential signal with 1 GΩ minimum input impedance. |+| 27 | AIN1 | input | Analog input 1; accepts ±20 V differential signal with 1 GΩ minimum input impedance. |+| 28 | GPIO3 | bidirectional | General-purpose input/output 3; programmable digital I/O with AVDD/AGND logic levels. |+| 29 | GPIO2 | bidirectional | General-purpose input/output 2; programmable digital I/O with AVDD/AGND logic levels. |+| 30 | REFN1/GPIO1 | bidirectional | Reference 1 negative input and GPIO 1; dual-function pin configurable as external reference or programmable I/O. |+| 31 | REFP1/GPIO0 | bidirectional | Reference 1 positive input and GPIO 0; dual-function pin configurable as external reference or programmable I/O. |+| 32 | REFN0 | input | Reference 0 negative input; differential reference voltage 0.9 V to AVDD V relative to REFP0. |+| 33 | Thermal pad | passive | Exposed thermal pad; connect to DGND for thermal and mechanical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Data Acquisition |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `ADS125H02IRHBR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `ads125h02irhbr-etched.step` / `ads125h02irhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads125h02irhbr.step` / `ads125h02irhbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads125h02) (89 pp, sha256 `76eb38f0ddf5fbdd`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads125h02irhbr-datasheet.pdf)
page.jsonadded+293@@ -0,0 +1,293 @@+{+ "slug": "ads125h02irhbr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADC), VQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads125h02irhbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads125h02irhbr.kicad_sym",+ "ads125h02irhbr.kicad_mod",+ "ads125h02irhbr.glb",+ "ads125h02irhbr.step",+ "ads125h02irhbr.lbr",+ "docs/hero.png",+ "docs/ads125h02irhbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADS125H02IRHBR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads125h02",+ "parts": {+ "symbol": "ads125h02irhbr.kicad_sym",+ "footprint": "ads125h02irhbr.kicad_mod",+ "model_3d": "ads125h02irhbr-etched.glb",+ "model_3d_plain": "ads125h02irhbr.glb",+ "model_3d_step": "ads125h02irhbr-etched.step",+ "model_3d_step_plain": "ads125h02irhbr.step",+ "lbr": "ads125h02irhbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2872153"+ },+ "pins": [+ {+ "number": "1",+ "name": "REFP0",+ "type": "input",+ "description": "Reference 0 positive input; differential reference voltage 0.9 V to AVDD V relative to REFN0."+ },+ {+ "number": "2",+ "name": "CAPP",+ "type": "output",+ "description": "PGA output positive; connect 1-nF C0G dielectric capacitor to CAPN for antialias filtering."+ },+ {+ "number": "3",+ "name": "CAPN",+ "type": "output",+ "description": "PGA output negative; connect 1-nF C0G dielectric capacitor to CAPP for antialias filtering."+ },+ {+ "number": "4",+ "name": "AVDD",+ "type": "power_in",+ "description": "Low-voltage analog power supply; nominal 5 V with operating range 4.75 V to 5.25 V."+ },+ {+ "number": "5",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the ADC ground plane for signal and power return."+ },+ {+ "number": "6",+ "name": "REFOUT",+ "type": "output",+ "description": "2.5-V internal reference output; connect 10-µF capacitor to AGND for noise filtering."+ },+ {+ "number": "7",+ "name": "RESET",+ "type": "input",+ "description": "Reset input active low; pulse low for minimum 4 fCLK cycles to reset device."+ },+ {+ "number": "8",+ "name": "START",+ "type": "input",+ "description": "Conversion start input active high; triggers single or continuous conversion based on mode."+ },+ {+ "number": "9",+ "name": "CS2",+ "type": "input",+ "description": "Serial interface chip select 2 active low; selects PGA registers for SPI communication."+ },+ {+ "number": "10",+ "name": "CS1",+ "type": "input",+ "description": "Serial interface chip select 1 active low; selects ADC registers for SPI communication."+ },+ {+ "number": "11",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input; 97 ns minimum period required for SPI interface with 40-60% duty cycle."+ },+ {+ "number": "12",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input; latched on SCLK falling edge with 25 ns minimum setup time."+ },+ {+ "number": "13",+ "name": "DRDY",+ "type": "output",+ "description": "Data-ready output active low; asserts when new conversion data are available for readback."+ },+ {+ "number": "14",+ "name": "DOUT/DRDY",+ "type": "tri_state",+ "description": "Serial data output and data-ready indicator in tri-state; functions as data output during read or DRDY signal between operations."+ },+ {+ "number": "15",+ "name": "BYPASS",+ "type": "output",+ "description": "2-V subregulator output; connect 1-µF capacitor to DGND for digital core supply decoupling."+ },+ {+ "number": "16",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground; connect to the ADC ground plane for digital signal return."+ },+ {+ "number": "17",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply; operating range 2.7 V to 5.25 V for digital I/O and core regulator."+ },+ {+ "number": "18",+ "name": "CLKIN",+ "type": "input",+ "description": "External clock input; connect to DGND for internal 7.3728 MHz oscillator operation."+ },+ {+ "number": "19",+ "name": "HV_AVSS",+ "type": "power_in",+ "description": "High-voltage negative analog power supply; operating range -18 V to 0 V relative to HV_AVDD."+ },+ {+ "number": "20",+ "name": "HV_AVDD",+ "type": "power_in",+ "description": "High-voltage positive analog power supply; operating range 5 V to 36 V for unipolar or ±5 V to ±18 V bipolar."+ },+ {+ "number": "21",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; electrically float or tie to AGND per application requirements."+ },+ {+ "number": "22",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; electrically float or tie to AGND per application requirements."+ },+ {+ "number": "23",+ "name": "IDAC2",+ "type": "output",+ "description": "Current source 2 output; provides 50 µA to 3000 µA programmable excitation current for sensor biasing."+ },+ {+ "number": "24",+ "name": "IDAC1",+ "type": "output",+ "description": "Current source 1 output; provides 50 µA to 3000 µA programmable excitation current for sensor biasing."+ },+ {+ "number": "25",+ "name": "AINCOM",+ "type": "input",+ "description": "Analog input common for single-ended measurements; 1 GΩ minimum input impedance to reference."+ },+ {+ "number": "26",+ "name": "AIN0",+ "type": "input",+ "description": "Analog input 0; accepts ±20 V differential signal with 1 GΩ minimum input impedance."+ },+ {+ "number": "27",+ "name": "AIN1",+ "type": "input",+ "description": "Analog input 1; accepts ±20 V differential signal with 1 GΩ minimum input impedance."+ },+ {+ "number": "28",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose input/output 3; programmable digital I/O with AVDD/AGND logic levels."+ },+ {+ "number": "29",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose input/output 2; programmable digital I/O with AVDD/AGND logic levels."+ },+ {+ "number": "30",+ "name": "REFN1/GPIO1",+ "type": "bidirectional",+ "description": "Reference 1 negative input and GPIO 1; dual-function pin configurable as external reference or programmable I/O."+ },+ {+ "number": "31",+ "name": "REFP1/GPIO0",+ "type": "bidirectional",+ "description": "Reference 1 positive input and GPIO 0; dual-function pin configurable as external reference or programmable I/O."+ },+ {+ "number": "32",+ "name": "REFN0",+ "type": "input",+ "description": "Reference 0 negative input; differential reference voltage 0.9 V to AVDD V relative to REFP0."+ },+ {+ "number": "33",+ "name": "Thermal pad",+ "type": "passive",+ "description": "Exposed thermal pad; connect to DGND for thermal and mechanical performance."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 14 (DOUT/DRDY) is a tri-state output with dual function: serial data output during read operatio; Pins 30 (REFN1/GPIO1) and 31 (REFP1/GPIO0) are multiplexed between analog reference inputs and GPIO ; HV_AVSS operates as high-voltage negative supply in bipolar mode (–18 V to 0 V) or ground reference "+ ],+ "pages_sent": 89,+ "cost_usd": 0.9583,+ "at": "2026-09-23T05:37:13"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads125h02",+ "pages": 89,+ "sha256": "76eb38f0ddf5fbdd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}