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ADS125H02IRHBR

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Texas Instruments Analog To Digital Converters (ADC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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ADS125H02IRHBR

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-32-EP(5x5)

ADS125H02IRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REFP0 input Reference 0 positive input; differential reference voltage 0.9 V to AVDD V relative to REFN0.
2 CAPP output PGA output positive; connect 1-nF C0G dielectric capacitor to CAPN for antialias filtering.
3 CAPN output PGA output negative; connect 1-nF C0G dielectric capacitor to CAPP for antialias filtering.
4 AVDD power_in Low-voltage analog power supply; nominal 5 V with operating range 4.75 V to 5.25 V.
5 AGND power_in Analog ground; connect to the ADC ground plane for signal and power return.
6 REFOUT output 2.5-V internal reference output; connect 10-µF capacitor to AGND for noise filtering.
7 RESET input Reset input active low; pulse low for minimum 4 fCLK cycles to reset device.
8 START input Conversion start input active high; triggers single or continuous conversion based on mode.
9 CS2 input Serial interface chip select 2 active low; selects PGA registers for SPI communication.
10 CS1 input Serial interface chip select 1 active low; selects ADC registers for SPI communication.
11 SCLK input Serial clock input; 97 ns minimum period required for SPI interface with 40-60% duty cycle.
12 DIN input Serial data input; latched on SCLK falling edge with 25 ns minimum setup time.
13 DRDY output Data-ready output active low; asserts when new conversion data are available for readback.
14 DOUT/DRDY tri_state Serial data output and data-ready indicator in tri-state; functions as data output during read or DRDY signal between operations.
15 BYPASS output 2-V subregulator output; connect 1-µF capacitor to DGND for digital core supply decoupling.
16 DGND power_in Digital ground; connect to the ADC ground plane for digital signal return.
17 DVDD power_in Digital power supply; operating range 2.7 V to 5.25 V for digital I/O and core regulator.
18 CLKIN input External clock input; connect to DGND for internal 7.3728 MHz oscillator operation.
19 HV_AVSS power_in High-voltage negative analog power supply; operating range -18 V to 0 V relative to HV_AVDD.
20 HV_AVDD power_in High-voltage positive analog power supply; operating range 5 V to 36 V for unipolar or ±5 V to ±18 V bipolar.
21 NC unconnected No connection; electrically float or tie to AGND per application requirements.
22 NC unconnected No connection; electrically float or tie to AGND per application requirements.
23 IDAC2 output Current source 2 output; provides 50 µA to 3000 µA programmable excitation current for sensor biasing.
24 IDAC1 output Current source 1 output; provides 50 µA to 3000 µA programmable excitation current for sensor biasing.
25 AINCOM input Analog input common for single-ended measurements; 1 GΩ minimum input impedance to reference.
26 AIN0 input Analog input 0; accepts ±20 V differential signal with 1 GΩ minimum input impedance.
27 AIN1 input Analog input 1; accepts ±20 V differential signal with 1 GΩ minimum input impedance.
28 GPIO3 bidirectional General-purpose input/output 3; programmable digital I/O with AVDD/AGND logic levels.
29 GPIO2 bidirectional General-purpose input/output 2; programmable digital I/O with AVDD/AGND logic levels.
30 REFN1/GPIO1 bidirectional Reference 1 negative input and GPIO 1; dual-function pin configurable as external reference or programmable I/O.
31 REFP1/GPIO0 bidirectional Reference 1 positive input and GPIO 0; dual-function pin configurable as external reference or programmable I/O.
32 REFN0 input Reference 0 negative input; differential reference voltage 0.9 V to AVDD V relative to REFP0.
33 Thermal pad passive Exposed thermal pad; connect to DGND for thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Data Acquisition
Pins 33

CAD (KiCad official)

  • Symbol: ADS125H02IRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ads125h02irhbr-etched.step / ads125h02irhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads125h02irhbr.step / ads125h02irhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 76eb38f0ddf5fbdd, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF