component
ADS1258IRTCT
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ADS1258IRTCT
Texas Instruments · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)
ADS1258IRTCT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN3 | input | Analog input 3 for single-ended channel 3 or differential channel 1 (-). |
| 2 | AIN2 | input | Analog input 2 for single-ended channel 2 or differential channel 1 (+). |
| 3 | AIN1 | input | Analog input 1 for single-ended channel 1 or differential channel 0 (-). |
| 4 | AIN0 | input | Analog input 0 for single-ended channel 0 or differential channel 0 (+). |
| 5 | AVSS | power_in | Negative analog power supply: 0V for unipolar operation or -2.5V for bipolar operation; internally connected to exposed thermal pad. |
| 6 | AVDD | power_in | Positive analog power supply: +5V for unipolar operation or +2.5V for bipolar operation. |
| 7 | PLLCAP | passive | PLL bypass capacitor connection point; connect 22nF capacitor to AVSS when using crystal oscillator. |
| 8 | XTAL1 | passive | 32.768kHz crystal oscillator input terminal 1. |
| 9 | XTAL2 | passive | 32.768kHz crystal oscillator input terminal 2. |
| 10 | PWDN | input | Power-down input; hold low for minimum of two fCLK cycles to engage low-power mode. |
| 11 | RESET | input | Reset input; hold low for minimum of two fCLK cycles to reset the device. |
| 12 | CLKSEL | input | Clock source select input; low activates crystal oscillator with clock output on CLKIO, high disables oscillator and applies external fCLK to CLKIO. |
| 13 | CLKIO | bidirectional | System clock input/output; serves as output when CLKSEL is low (crystal oscillator mode) or input when CLKSEL is high (external clock mode). |
| 14 | GPIO0 | bidirectional | General-purpose digital input/output 0; programmable as input or output via register settings. |
| 15 | GPIO1 | bidirectional | General-purpose digital input/output 1; programmable as input or output via register settings. |
| 16 | GPIO2 | bidirectional | General-purpose digital input/output 2; programmable as input or output via register settings. |
| 17 | GPIO3 | bidirectional | General-purpose digital input/output 3; programmable as input or output via register settings. |
| 18 | GPIO4 | bidirectional | General-purpose digital input/output 4; programmable as input or output via register settings. |
| 19 | GPIO5 | bidirectional | General-purpose digital input/output 5; programmable as input or output via register settings. |
| 20 | GPIO6 | bidirectional | General-purpose digital input/output 6; programmable as input or output via register settings. |
| 21 | GPIO7 | bidirectional | General-purpose digital input/output 7; programmable as input or output via register settings. |
| 22 | SCLK | input | SPI clock input; data clocked in on rising edge and clocked out on falling edge. |
| 23 | DIN | input | SPI data input; serial data is input to the device via this pin. |
| 24 | DOUT | output | SPI data output; serial data is output from the device; tri-states high when CS is inactive. |
| 25 | DRDY | output | Data ready output; active low when new conversion data is available. |
| 26 | START | input | Start conversion input; active high to initiate analog-to-digital conversion. |
| 27 | CS | input | SPI chip select input; active low to enable SPI communication, can be tied low for continuous operation. |
| 28 | DVDD | power_in | Digital power supply; operates at 2.7V to 5.25V. |
| 29 | DGND | power_in | Digital ground connection. |
| 30 | VREFN | input | Reference input negative; recommend 10μF tantalum with 0.1μF ceramic capacitor across reference pins for rated performance. |
| 31 | VREFP | input | Reference input positive; recommend 10μF tantalum with 0.1μF ceramic capacitor across reference pins for rated performance. |
| 32 | AINCOM | input | Analog input common; common reference point connected to all single-ended analog inputs. |
| 33 | AIN15 | input | Analog input 15 for single-ended channel 15 or differential channel 7 (-). |
| 34 | AIN14 | input | Analog input 14 for single-ended channel 14 or differential channel 7 (+). |
| 35 | AIN13 | input | Analog input 13 for single-ended channel 13 or differential channel 6 (-). |
| 36 | AIN12 | input | Analog input 12 for single-ended channel 12 or differential channel 6 (+). |
| 37 | AIN11 | input | Analog input 11 for single-ended channel 11 or differential channel 5 (-). |
| 38 | AIN10 | input | Analog input 10 for single-ended channel 10 or differential channel 5 (+). |
| 39 | AIN9 | input | Analog input 9 for single-ended channel 9 or differential channel 4 (-). |
| 40 | AIN8 | input | Analog input 8 for single-ended channel 8 or differential channel 4 (+). |
| 41 | ADCINN | input | ADC differential input negative; part of external multiplexer output signal conditioning path. |
| 42 | ADCINP | input | ADC differential input positive; part of external multiplexer output signal conditioning path. |
| 43 | MUXOUTN | output | Multiplexer differential output negative; accessible for external signal conditioning prior to ADC input. |
| 44 | MUXOUTP | output | Multiplexer differential output positive; accessible for external signal conditioning prior to ADC input. |
| 45 | AIN7 | input | Analog input 7 for single-ended channel 7 or differential channel 3 (-). |
| 46 | AIN6 | input | Analog input 6 for single-ended channel 6 or differential channel 3 (+). |
| 47 | AIN5 | input | Analog input 5 for single-ended channel 5 or differential channel 2 (-). |
| 48 | AIN4 | input | Analog input 4 for single-ended channel 4 or differential channel 2 (+). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Data Acquisition |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
ADS1258IRTCT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ads1258irtct-etched.step/ads1258irtct-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads1258irtct.step/ads1258irtct.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
469eda615665f3b4, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADS1258IRTCT
**Texas Instruments** · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)
ADS1258IRTCT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN3 | input | Analog input 3 for single-ended channel 3 or differential channel 1 (-). |
| 2 | AIN2 | input | Analog input 2 for single-ended channel 2 or differential channel 1 (+). |
| 3 | AIN1 | input | Analog input 1 for single-ended channel 1 or differential channel 0 (-). |
| 4 | AIN0 | input | Analog input 0 for single-ended channel 0 or differential channel 0 (+). |
| 5 | AVSS | power_in | Negative analog power supply: 0V for unipolar operation or -2.5V for bipolar operation; internally connected to exposed thermal pad. |
| 6 | AVDD | power_in | Positive analog power supply: +5V for unipolar operation or +2.5V for bipolar operation. |
| 7 | PLLCAP | passive | PLL bypass capacitor connection point; connect 22nF capacitor to AVSS when using crystal oscillator. |
| 8 | XTAL1 | passive | 32.768kHz crystal oscillator input terminal 1. |
| 9 | XTAL2 | passive | 32.768kHz crystal oscillator input terminal 2. |
| 10 | PWDN | input | Power-down input; hold low for minimum of two fCLK cycles to engage low-power mode. |
| 11 | RESET | input | Reset input; hold low for minimum of two fCLK cycles to reset the device. |
| 12 | CLKSEL | input | Clock source select input; low activates crystal oscillator with clock output on CLKIO, high disables oscillator and applies external fCLK to CLKIO. |
| 13 | CLKIO | bidirectional | System clock input/output; serves as output when CLKSEL is low (crystal oscillator mode) or input when CLKSEL is high (external clock mode). |
| 14 | GPIO0 | bidirectional | General-purpose digital input/output 0; programmable as input or output via register settings. |
| 15 | GPIO1 | bidirectional | General-purpose digital input/output 1; programmable as input or output via register settings. |
| 16 | GPIO2 | bidirectional | General-purpose digital input/output 2; programmable as input or output via register settings. |
| 17 | GPIO3 | bidirectional | General-purpose digital input/output 3; programmable as input or output via register settings. |
| 18 | GPIO4 | bidirectional | General-purpose digital input/output 4; programmable as input or output via register settings. |
| 19 | GPIO5 | bidirectional | General-purpose digital input/output 5; programmable as input or output via register settings. |
| 20 | GPIO6 | bidirectional | General-purpose digital input/output 6; programmable as input or output via register settings. |
| 21 | GPIO7 | bidirectional | General-purpose digital input/output 7; programmable as input or output via register settings. |
| 22 | SCLK | input | SPI clock input; data clocked in on rising edge and clocked out on falling edge. |
| 23 | DIN | input | SPI data input; serial data is input to the device via this pin. |
| 24 | DOUT | output | SPI data output; serial data is output from the device; tri-states high when CS is inactive. |
| 25 | DRDY | output | Data ready output; active low when new conversion data is available. |
| 26 | START | input | Start conversion input; active high to initiate analog-to-digital conversion. |
| 27 | CS | input | SPI chip select input; active low to enable SPI communication, can be tied low for continuous operation. |
| 28 | DVDD | power_in | Digital power supply; operates at 2.7V to 5.25V. |
| 29 | DGND | power_in | Digital ground connection. |
| 30 | VREFN | input | Reference input negative; recommend 10μF tantalum with 0.1μF ceramic capacitor across reference pins for rated performance. |
| 31 | VREFP | input | Reference input positive; recommend 10μF tantalum with 0.1μF ceramic capacitor across reference pins for rated performance. |
| 32 | AINCOM | input | Analog input common; common reference point connected to all single-ended analog inputs. |
| 33 | AIN15 | input | Analog input 15 for single-ended channel 15 or differential channel 7 (-). |
| 34 | AIN14 | input | Analog input 14 for single-ended channel 14 or differential channel 7 (+). |
| 35 | AIN13 | input | Analog input 13 for single-ended channel 13 or differential channel 6 (-). |
| 36 | AIN12 | input | Analog input 12 for single-ended channel 12 or differential channel 6 (+). |
| 37 | AIN11 | input | Analog input 11 for single-ended channel 11 or differential channel 5 (-). |
| 38 | AIN10 | input | Analog input 10 for single-ended channel 10 or differential channel 5 (+). |
| 39 | AIN9 | input | Analog input 9 for single-ended channel 9 or differential channel 4 (-). |
| 40 | AIN8 | input | Analog input 8 for single-ended channel 8 or differential channel 4 (+). |
| 41 | ADCINN | input | ADC differential input negative; part of external multiplexer output signal conditioning path. |
| 42 | ADCINP | input | ADC differential input positive; part of external multiplexer output signal conditioning path. |
| 43 | MUXOUTN | output | Multiplexer differential output negative; accessible for external signal conditioning prior to ADC input. |
| 44 | MUXOUTP | output | Multiplexer differential output positive; accessible for external signal conditioning prior to ADC input. |
| 45 | AIN7 | input | Analog input 7 for single-ended channel 7 or differential channel 3 (-). |
| 46 | AIN6 | input | Analog input 6 for single-ended channel 6 or differential channel 3 (+). |
| 47 | AIN5 | input | Analog input 5 for single-ended channel 5 or differential channel 2 (-). |
| 48 | AIN4 | input | Analog input 4 for single-ended channel 4 or differential channel 2 (+). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Data Acquisition |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `ADS1258IRTCT`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `ads1258irtct-etched.step` / `ads1258irtct-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1258irtct.step` / `ads1258irtct.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1258) (55 pp, sha256 `469eda615665f3b4`, retrieved 2026-10-03, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ads1258irtct-datasheet.pdf)