component

ADS1258IRTCR

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionads1258irtcrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ads1258irtcr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers ads1258irtcr: viewers · Ray 1mo ago
ads1258irtcr-etched.fit.json ads1258irtcr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1258irtcr-etched.glb ads1258irtcr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1258irtcr-etched.step ads1258irtcr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1258irtcr.glb Publish 0.1.0 · Ray 1mo ago
ads1258irtcr.kicad_mod Publish 0.1.0 · Ray 1mo ago
ads1258irtcr.kicad_sym Publish 0.1.0 · Ray 1mo ago
ads1258irtcr.lbr Publish 0.1.0 · Ray 1mo ago
ads1258irtcr.step Publish 0.1.0 · Ray 1mo ago
package.json ads1258irtcr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json ads1258irtcr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md Initial commit: component/ads1258irtcr · Ray 1mo ago

ADS1258IRTCR

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)

ADS1258IRTCR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN3 input Analog Input 3: Single-Ended Channel 3 or Differential Channel 1 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
2 AIN2 input Analog Input 2: Single-Ended Channel 2 or Differential Channel 1 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
3 AIN1 input Analog Input 1: Single-Ended Channel 1 or Differential Channel 0 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
4 AIN0 input Analog Input 0: Single-Ended Channel 0 or Differential Channel 0 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
5 AVSS power_in Negative Analog Power Supply: 0V for unipolar operation or -2.5V for bipolar operation, internally connected to exposed thermal pad of QFN package.
6 AVDD power_in Positive Analog Power Supply: +5V for unipolar operation or +2.5V for bipolar operation.
7 PLLCAP passive PLL Bypass Capacitor: connect 22nF capacitor to AVSS when using crystal oscillator.
8 XTAL1 bidirectional 32.768kHz Crystal Oscillator Input 1; connect parallel resonant crystal (CL = 12.5pF, ESR ≤ 35kΩ) for system clock generation.
9 XTAL2 bidirectional 32.768kHz Crystal Oscillator Input 2; connect parallel resonant crystal (CL = 12.5pF, ESR ≤ 35kΩ) for system clock generation.
10 PWDN input Power-Down Input: hold low for minimum of two fCLK cycles to engage low-power mode with all internal circuitry disabled.
11 RESET input Reset Input: hold low for minimum of two fCLK cycles to reset device and clear digital filter.
12 CLKSEL input Clock Select Input: low activates crystal oscillator with fCLK output on CLKIO, high disables oscillator and requires fCLK (16MHz typical) applied to CLKIO.
13 CLKIO bidirectional System Clock Input/Output: accepts external clock 0.1-16MHz (duty cycle 40-60%) when CLKSEL=1, or outputs 15.729MHz clock when CLKSEL=0.
14 GPIO0 bidirectional General-Purpose Digital Input/Output 0: individually configurable as input or output via GPIOC register bit 0, level controlled via GPIOD register.
15 GPIO1 bidirectional General-Purpose Digital Input/Output 1: individually configurable as input or output via GPIOC register bit 1, level controlled via GPIOD register.
16 GPIO2 bidirectional General-Purpose Digital Input/Output 2: individually configurable as input or output via GPIOC register bit 2, level controlled via GPIOD register.
17 GPIO3 bidirectional General-Purpose Digital Input/Output 3: individually configurable as input or output via GPIOC register bit 3, level controlled via GPIOD register.
18 GPIO4 bidirectional General-Purpose Digital Input/Output 4: individually configurable as input or output via GPIOC register bit 4, level controlled via GPIOD register.
19 GPIO5 bidirectional General-Purpose Digital Input/Output 5: individually configurable as input or output via GPIOC register bit 5, level controlled via GPIOD register.
20 GPIO6 bidirectional General-Purpose Digital Input/Output 6: individually configurable as input or output via GPIOC register bit 6, level controlled via GPIOD register.
21 GPIO7 bidirectional General-Purpose Digital Input/Output 7: individually configurable as input or output via GPIOC register bit 7, level controlled via GPIOD register.
22 SCLK input SPI Interface Clock Input: data clocked in on rising edge and clocked out on falling edge, input frequency 0.1-16MHz with duty cycle 40-60%.
23 DIN input SPI Interface Data Input: serial data is input to device on rising edge of SCLK.
24 DOUT output SPI Interface Data Output: serial data is output from device on falling edge of SCLK, tri-states when CS=1.
25 DRDY output Data Ready Output: active low output asserts when new channel data is available, returns high after first falling edge of SCLK during data read.
26 START input Start Conversion Input: active high input that starts conversion when high and stops conversion when low (device completes current conversion).
27 CS input SPI Interface Chip Select Input: active low input that selects device for serial communication, aborts operations and resets SPI interface when high.
28 DVDD power_in Digital Power Supply: 2.7V to 5.25V, requires 10µF tantalum bypassed with 0.1µF ceramic capacitor close to pins.
29 DGND power_in Digital Ground: return path for digital supply current.
30 VREFN input Reference Input Negative: accepts reference voltage from AVSS - 0.1V to VREFP - 0.5V with input impedance 40kΩ.
31 VREFP input Reference Input Positive: accepts reference voltage from VREFN + 0.5V to AVDD + 0.1V with input impedance 40kΩ.
32 AINCOM input Analog Input Common: common reference input for all single-ended measurements, can be set from AVSS - 100mV to AVDD + 100mV.
33 AIN15 input Analog Input 15: Single-Ended Channel 15 or Differential Channel 7 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
34 AIN14 input Analog Input 14: Single-Ended Channel 14 or Differential Channel 7 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
35 AIN13 input Analog Input 13: Single-Ended Channel 13 or Differential Channel 6 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
36 AIN12 input Analog Input 12: Single-Ended Channel 12 or Differential Channel 6 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
37 AIN11 input Analog Input 11: Single-Ended Channel 11 or Differential Channel 5 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
38 AIN10 input Analog Input 10: Single-Ended Channel 10 or Differential Channel 5 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
39 AIN9 input Analog Input 9: Single-Ended Channel 9 or Differential Channel 4 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
40 AIN8 input Analog Input 8: Single-Ended Channel 8 or Differential Channel 4 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
41 ADCINN input ADC Differential Input (-): negative ADC input accepts signals from external multiplexer loop or internal connection, voltage limited to AVSS - 100mV to AVDD + 100mV.
42 ADCINP input ADC Differential Input (+): positive ADC input accepts signals from external multiplexer loop or internal connection, voltage limited to AVSS - 100mV to AVDD + 100mV.
43 MUXOUTN output Multiplexer Differential Output (-): negative output of input multiplexer for external signal conditioning, accessible for buffering or filtering.
44 MUXOUTP output Multiplexer Differential Output (+): positive output of input multiplexer for external signal conditioning, accessible for buffering or filtering.
45 AIN7 input Analog Input 7: Single-Ended Channel 7 or Differential Channel 3 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
46 AIN6 input Analog Input 6: Single-Ended Channel 6 or Differential Channel 3 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
47 AIN5 input Analog Input 5: Single-Ended Channel 5 or Differential Channel 2 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV.
48 AIN4 input Analog Input 4: Single-Ended Channel 4 or Differential Channel 2 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Data Acquisition
Pins 49

CAD (KiCad official)

  • Symbol: ADS1258IRTCR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads1258irtcr-etched.step / ads1258irtcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1258irtcr.step / ads1258irtcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 469eda615665f3b4, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF