component
ADS1258IRTCR
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Texas Instruments Analog To Digital Converters (ADC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# ADS1258IRTCR++**Texas Instruments** · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)++ADS1258IRTCR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AIN3 | input | Analog Input 3: Single-Ended Channel 3 or Differential Channel 1 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 2 | AIN2 | input | Analog Input 2: Single-Ended Channel 2 or Differential Channel 1 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 3 | AIN1 | input | Analog Input 1: Single-Ended Channel 1 or Differential Channel 0 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 4 | AIN0 | input | Analog Input 0: Single-Ended Channel 0 or Differential Channel 0 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 5 | AVSS | power_in | Negative Analog Power Supply: 0V for unipolar operation or -2.5V for bipolar operation, internally connected to exposed thermal pad of QFN package. |+| 6 | AVDD | power_in | Positive Analog Power Supply: +5V for unipolar operation or +2.5V for bipolar operation. |+| 7 | PLLCAP | passive | PLL Bypass Capacitor: connect 22nF capacitor to AVSS when using crystal oscillator. |+| 8 | XTAL1 | bidirectional | 32.768kHz Crystal Oscillator Input 1; connect parallel resonant crystal (CL = 12.5pF, ESR ≤ 35kΩ) for system clock generation. |+| 9 | XTAL2 | bidirectional | 32.768kHz Crystal Oscillator Input 2; connect parallel resonant crystal (CL = 12.5pF, ESR ≤ 35kΩ) for system clock generation. |+| 10 | PWDN | input | Power-Down Input: hold low for minimum of two fCLK cycles to engage low-power mode with all internal circuitry disabled. |+| 11 | RESET | input | Reset Input: hold low for minimum of two fCLK cycles to reset device and clear digital filter. |+| 12 | CLKSEL | input | Clock Select Input: low activates crystal oscillator with fCLK output on CLKIO, high disables oscillator and requires fCLK (16MHz typical) applied to CLKIO. |+| 13 | CLKIO | bidirectional | System Clock Input/Output: accepts external clock 0.1-16MHz (duty cycle 40-60%) when CLKSEL=1, or outputs 15.729MHz clock when CLKSEL=0. |+| 14 | GPIO0 | bidirectional | General-Purpose Digital Input/Output 0: individually configurable as input or output via GPIOC register bit 0, level controlled via GPIOD register. |+| 15 | GPIO1 | bidirectional | General-Purpose Digital Input/Output 1: individually configurable as input or output via GPIOC register bit 1, level controlled via GPIOD register. |+| 16 | GPIO2 | bidirectional | General-Purpose Digital Input/Output 2: individually configurable as input or output via GPIOC register bit 2, level controlled via GPIOD register. |+| 17 | GPIO3 | bidirectional | General-Purpose Digital Input/Output 3: individually configurable as input or output via GPIOC register bit 3, level controlled via GPIOD register. |+| 18 | GPIO4 | bidirectional | General-Purpose Digital Input/Output 4: individually configurable as input or output via GPIOC register bit 4, level controlled via GPIOD register. |+| 19 | GPIO5 | bidirectional | General-Purpose Digital Input/Output 5: individually configurable as input or output via GPIOC register bit 5, level controlled via GPIOD register. |+| 20 | GPIO6 | bidirectional | General-Purpose Digital Input/Output 6: individually configurable as input or output via GPIOC register bit 6, level controlled via GPIOD register. |+| 21 | GPIO7 | bidirectional | General-Purpose Digital Input/Output 7: individually configurable as input or output via GPIOC register bit 7, level controlled via GPIOD register. |+| 22 | SCLK | input | SPI Interface Clock Input: data clocked in on rising edge and clocked out on falling edge, input frequency 0.1-16MHz with duty cycle 40-60%. |+| 23 | DIN | input | SPI Interface Data Input: serial data is input to device on rising edge of SCLK. |+| 24 | DOUT | output | SPI Interface Data Output: serial data is output from device on falling edge of SCLK, tri-states when CS=1. |+| 25 | DRDY | output | Data Ready Output: active low output asserts when new channel data is available, returns high after first falling edge of SCLK during data read. |+| 26 | START | input | Start Conversion Input: active high input that starts conversion when high and stops conversion when low (device completes current conversion). |+| 27 | CS | input | SPI Interface Chip Select Input: active low input that selects device for serial communication, aborts operations and resets SPI interface when high. |+| 28 | DVDD | power_in | Digital Power Supply: 2.7V to 5.25V, requires 10µF tantalum bypassed with 0.1µF ceramic capacitor close to pins. |+| 29 | DGND | power_in | Digital Ground: return path for digital supply current. |+| 30 | VREFN | input | Reference Input Negative: accepts reference voltage from AVSS - 0.1V to VREFP - 0.5V with input impedance 40kΩ. |+| 31 | VREFP | input | Reference Input Positive: accepts reference voltage from VREFN + 0.5V to AVDD + 0.1V with input impedance 40kΩ. |+| 32 | AINCOM | input | Analog Input Common: common reference input for all single-ended measurements, can be set from AVSS - 100mV to AVDD + 100mV. |+| 33 | AIN15 | input | Analog Input 15: Single-Ended Channel 15 or Differential Channel 7 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 34 | AIN14 | input | Analog Input 14: Single-Ended Channel 14 or Differential Channel 7 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 35 | AIN13 | input | Analog Input 13: Single-Ended Channel 13 or Differential Channel 6 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 36 | AIN12 | input | Analog Input 12: Single-Ended Channel 12 or Differential Channel 6 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 37 | AIN11 | input | Analog Input 11: Single-Ended Channel 11 or Differential Channel 5 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 38 | AIN10 | input | Analog Input 10: Single-Ended Channel 10 or Differential Channel 5 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 39 | AIN9 | input | Analog Input 9: Single-Ended Channel 9 or Differential Channel 4 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 40 | AIN8 | input | Analog Input 8: Single-Ended Channel 8 or Differential Channel 4 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 41 | ADCINN | input | ADC Differential Input (-): negative ADC input accepts signals from external multiplexer loop or internal connection, voltage limited to AVSS - 100mV to AVDD + 100mV. |+| 42 | ADCINP | input | ADC Differential Input (+): positive ADC input accepts signals from external multiplexer loop or internal connection, voltage limited to AVSS - 100mV to AVDD + 100mV. |+| 43 | MUXOUTN | output | Multiplexer Differential Output (-): negative output of input multiplexer for external signal conditioning, accessible for buffering or filtering. |+| 44 | MUXOUTP | output | Multiplexer Differential Output (+): positive output of input multiplexer for external signal conditioning, accessible for buffering or filtering. |+| 45 | AIN7 | input | Analog Input 7: Single-Ended Channel 7 or Differential Channel 3 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 46 | AIN6 | input | Analog Input 6: Single-Ended Channel 6 or Differential Channel 3 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 47 | AIN5 | input | Analog Input 5: Single-Ended Channel 5 or Differential Channel 2 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 48 | AIN4 | input | Analog Input 4: Single-Ended Channel 4 or Differential Channel 2 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Data Acquisition |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `ADS1258IRTCR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `ads1258irtcr-etched.step` / `ads1258irtcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1258irtcr.step` / `ads1258irtcr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1258) (55 pp, sha256 `469eda615665f3b4`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads1258irtcr-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads1258irtcr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads1258irtcr.kicad_sym",+ "ads1258irtcr.kicad_mod",+ "ads1258irtcr.glb",+ "ads1258irtcr.step",+ "ads1258irtcr.lbr",+ "docs/hero.png",+ "docs/ads1258irtcr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADS1258IRTCR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads1258",+ "parts": {+ "symbol": "ads1258irtcr.kicad_sym",+ "footprint": "ads1258irtcr.kicad_mod",+ "model_3d": "ads1258irtcr-etched.glb",+ "model_3d_plain": "ads1258irtcr.glb",+ "model_3d_step": "ads1258irtcr-etched.step",+ "model_3d_step_plain": "ads1258irtcr.step",+ "lbr": "ads1258irtcr.lbr"+ },+ "distributor_links": {+ "lcsc": "C527439"+ },+ "pins": [+ {+ "number": "1",+ "name": "AIN3",+ "type": "input",+ "description": "Analog Input 3: Single-Ended Channel 3 or Differential Channel 1 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "2",+ "name": "AIN2",+ "type": "input",+ "description": "Analog Input 2: Single-Ended Channel 2 or Differential Channel 1 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "3",+ "name": "AIN1",+ "type": "input",+ "description": "Analog Input 1: Single-Ended Channel 1 or Differential Channel 0 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "4",+ "name": "AIN0",+ "type": "input",+ "description": "Analog Input 0: Single-Ended Channel 0 or Differential Channel 0 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "5",+ "name": "AVSS",+ "type": "power_in",+ "description": "Negative Analog Power Supply: 0V for unipolar operation or -2.5V for bipolar operation, internally connected to exposed thermal pad of QFN package."+ },+ {+ "number": "6",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive Analog Power Supply: +5V for unipolar operation or +2.5V for bipolar operation."+ },+ {+ "number": "7",+ "name": "PLLCAP",+ "type": "passive",+ "description": "PLL Bypass Capacitor: connect 22nF capacitor to AVSS when using crystal oscillator."+ },+ {+ "number": "8",+ "name": "XTAL1",+ "type": "bidirectional",+ "description": "32.768kHz Crystal Oscillator Input 1; connect parallel resonant crystal (CL = 12.5pF, ESR ≤ 35kΩ) for system clock generation."+ },+ {+ "number": "9",+ "name": "XTAL2",+ "type": "bidirectional",+ "description": "32.768kHz Crystal Oscillator Input 2; connect parallel resonant crystal (CL = 12.5pF, ESR ≤ 35kΩ) for system clock generation."+ },+ {+ "number": "10",+ "name": "PWDN",+ "type": "input",+ "description": "Power-Down Input: hold low for minimum of two fCLK cycles to engage low-power mode with all internal circuitry disabled."+ },+ {+ "number": "11",+ "name": "RESET",+ "type": "input",+ "description": "Reset Input: hold low for minimum of two fCLK cycles to reset device and clear digital filter."+ },+ {+ "number": "12",+ "name": "CLKSEL",+ "type": "input",+ "description": "Clock Select Input: low activates crystal oscillator with fCLK output on CLKIO, high disables oscillator and requires fCLK (16MHz typical) applied to CLKIO."+ },+ {+ "number": "13",+ "name": "CLKIO",+ "type": "bidirectional",+ "description": "System Clock Input/Output: accepts external clock 0.1-16MHz (duty cycle 40-60%) when CLKSEL=1, or outputs 15.729MHz clock when CLKSEL=0."+ },+ {+ "number": "14",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 0: individually configurable as input or output via GPIOC register bit 0, level controlled via GPIOD register."+ },+ {+ "number": "15",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 1: individually configurable as input or output via GPIOC register bit 1, level controlled via GPIOD register."+ },+ {+ "number": "16",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 2: individually configurable as input or output via GPIOC register bit 2, level controlled via GPIOD register."+ },+ {+ "number": "17",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 3: individually configurable as input or output via GPIOC register bit 3, level controlled via GPIOD register."+ },+ {+ "number": "18",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 4: individually configurable as input or output via GPIOC register bit 4, level controlled via GPIOD register."+ },+ {+ "number": "19",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 5: individually configurable as input or output via GPIOC register bit 5, level controlled via GPIOD register."+ },+ {+ "number": "20",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 6: individually configurable as input or output via GPIOC register bit 6, level controlled via GPIOD register."+ },+ {+ "number": "21",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-Purpose Digital Input/Output 7: individually configurable as input or output via GPIOC register bit 7, level controlled via GPIOD register."+ },+ {+ "number": "22",+ "name": "SCLK",+ "type": "input",+ "description": "SPI Interface Clock Input: data clocked in on rising edge and clocked out on falling edge, input frequency 0.1-16MHz with duty cycle 40-60%."+ },+ {+ "number": "23",+ "name": "DIN",+ "type": "input",+ "description": "SPI Interface Data Input: serial data is input to device on rising edge of SCLK."+ },+ {+ "number": "24",+ "name": "DOUT",+ "type": "output",+ "description": "SPI Interface Data Output: serial data is output from device on falling edge of SCLK, tri-states when CS=1."+ },+ {+ "number": "25",+ "name": "DRDY",+ "type": "output",+ "description": "Data Ready Output: active low output asserts when new channel data is available, returns high after first falling edge of SCLK during data read."+ },+ {+ "number": "26",+ "name": "START",+ "type": "input",+ "description": "Start Conversion Input: active high input that starts conversion when high and stops conversion when low (device completes current conversion)."+ },+ {+ "number": "27",+ "name": "CS",+ "type": "input",+ "description": "SPI Interface Chip Select Input: active low input that selects device for serial communication, aborts operations and resets SPI interface when high."+ },+ {+ "number": "28",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital Power Supply: 2.7V to 5.25V, requires 10µF tantalum bypassed with 0.1µF ceramic capacitor close to pins."+ },+ {+ "number": "29",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground: return path for digital supply current."+ },+ {+ "number": "30",+ "name": "VREFN",+ "type": "input",+ "description": "Reference Input Negative: accepts reference voltage from AVSS - 0.1V to VREFP - 0.5V with input impedance 40kΩ."+ },+ {+ "number": "31",+ "name": "VREFP",+ "type": "input",+ "description": "Reference Input Positive: accepts reference voltage from VREFN + 0.5V to AVDD + 0.1V with input impedance 40kΩ."+ },+ {+ "number": "32",+ "name": "AINCOM",+ "type": "input",+ "description": "Analog Input Common: common reference input for all single-ended measurements, can be set from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "33",+ "name": "AIN15",+ "type": "input",+ "description": "Analog Input 15: Single-Ended Channel 15 or Differential Channel 7 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "34",+ "name": "AIN14",+ "type": "input",+ "description": "Analog Input 14: Single-Ended Channel 14 or Differential Channel 7 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "35",+ "name": "AIN13",+ "type": "input",+ "description": "Analog Input 13: Single-Ended Channel 13 or Differential Channel 6 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "36",+ "name": "AIN12",+ "type": "input",+ "description": "Analog Input 12: Single-Ended Channel 12 or Differential Channel 6 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "37",+ "name": "AIN11",+ "type": "input",+ "description": "Analog Input 11: Single-Ended Channel 11 or Differential Channel 5 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "38",+ "name": "AIN10",+ "type": "input",+ "description": "Analog Input 10: Single-Ended Channel 10 or Differential Channel 5 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "39",+ "name": "AIN9",+ "type": "input",+ "description": "Analog Input 9: Single-Ended Channel 9 or Differential Channel 4 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "40",+ "name": "AIN8",+ "type": "input",+ "description": "Analog Input 8: Single-Ended Channel 8 or Differential Channel 4 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "41",+ "name": "ADCINN",+ "type": "input",+ "description": "ADC Differential Input (-): negative ADC input accepts signals from external multiplexer loop or internal connection, voltage limited to AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "42",+ "name": "ADCINP",+ "type": "input",+ "description": "ADC Differential Input (+): positive ADC input accepts signals from external multiplexer loop or internal connection, voltage limited to AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "43",+ "name": "MUXOUTN",+ "type": "output",+ "description": "Multiplexer Differential Output (-): negative output of input multiplexer for external signal conditioning, accessible for buffering or filtering."+ },+ {+ "number": "44",+ "name": "MUXOUTP",+ "type": "output",+ "description": "Multiplexer Differential Output (+): positive output of input multiplexer for external signal conditioning, accessible for buffering or filtering."+ },+ {+ "number": "45",+ "name": "AIN7",+ "type": "input",+ "description": "Analog Input 7: Single-Ended Channel 7 or Differential Channel 3 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "46",+ "name": "AIN6",+ "type": "input",+ "description": "Analog Input 6: Single-Ended Channel 6 or Differential Channel 3 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "47",+ "name": "AIN5",+ "type": "input",+ "description": "Analog Input 5: Single-Ended Channel 5 or Differential Channel 2 (-), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "48",+ "name": "AIN4",+ "type": "input",+ "description": "Analog Input 4: Single-Ended Channel 4 or Differential Channel 2 (+), accepts input signals from AVSS - 100mV to AVDD + 100mV."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 55,+ "cost_usd": 0.6413,+ "at": "2026-09-23T00:20:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads1258",+ "pages": 55,+ "sha256": "469eda615665f3b4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}