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ADS124S06IPBSR

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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS124S06IPBSR

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(5x5)

ADS124S06IPBSR from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AINCOM input Common analog input for single-ended measurements operating within AVSS - 0.3V to AVDD + 0.3V.
2 AIN5 input Analog input 5 for multiplexed conversion operating within AVSS - 0.3V to AVDD + 0.3V.
3 AIN4 input Analog input 4 for multiplexed conversion operating within AVSS - 0.3V to AVDD + 0.3V.
4 AIN3 input Analog input 3 for multiplexed conversion operating within AVSS - 0.3V to AVDD + 0.3V.
5 AIN2 input Analog input 2 for multiplexed conversion operating within AVSS - 0.3V to AVDD + 0.3V.
6 AIN1 input Analog input 1 for multiplexed conversion operating within AVSS - 0.3V to AVDD + 0.3V.
7 AIN0 input Analog input 0 for multiplexed conversion operating within AVSS - 0.3V to AVDD + 0.3V.
8 START/SYNC input Digital start conversion or synchronization input with logic levels from DGND - 0.3V to IOVDD + 0.3V.
9 CS input Active-low chip select enabling serial interface operation with logic levels from DGND - 0.3V to IOVDD + 0.3V.
10 DIN input Serial data input latched on SCLK falling edge with logic levels from DGND - 0.3V to IOVDD + 0.3V.
11 SCLK input Serial clock input for data synchronization with logic levels from DGND - 0.3V to IOVDD + 0.3V.
12 DOUT/DRDY tri_state Serial data output and data-ready indicator (active low) that tri-states (high-impedance) when CS is high.
13 DRDY output Data-ready output (active low) indicating when conversion data are ready for retrieval.
14 DGND power_in Digital ground for digital core and I/O circuits.
15 IOVDD power_in Digital I/O power supply (2.7V to 3.6V) requiring 100nF minimum bypass capacitor to DGND when not tied to DVDD.
16 DVDD power_in Digital core power supply (2.7V to 3.6V) requiring 100nF minimum bypass capacitor to DGND.
17 CLK input External clock input (DGND - 0.3V to IOVDD + 0.3V) that connects to DGND for internal oscillator operation.
18 RESET input Active-low reset input with logic levels from DGND - 0.3V to IOVDD + 0.3V.
19 GPIO3/AIN11 bidirectional Configurable general-purpose I/O using analog supply logic levels, with analog input 11 function not available on ADS124S06.
20 GPIO2/AIN10 bidirectional Configurable general-purpose I/O using analog supply logic levels, with analog input 10 function not available on ADS124S06.
21 GPIO1/AIN9 bidirectional Configurable general-purpose I/O using analog supply logic levels, with analog input 9 function not available on ADS124S06.
22 GPIO0/AIN8 bidirectional Configurable general-purpose I/O using analog supply logic levels, with analog input 8 function not available on ADS124S06.
23 REFOUT output Positive voltage reference output requiring 1µF to 47µF bypass capacitor to REFCOM when internal reference is enabled.
24 REFCOM output Negative voltage reference output that connects to AVSS.
25 NC unconnected No-connect pin that should be left unconnected or optionally connected to AVSS.
26 AVDD power_in Positive analog power supply (2.7V to 5.25V) requiring 330nF minimum bypass capacitor to AVSS.
27 AVSS power_in Negative analog power supply and ground reference for analog circuits.
28 AVSS-SW power_in Negative analog power supply low-side switch that connects to AVSS.
29 REFN0 input Negative external reference input 0 operating within AVSS - 0.3V to AVDD + 0.3V.
30 REFP0 input Positive external reference input 0 operating within AVSS - 0.3V to AVDD + 0.3V.
31 REFN1/AIN7 input Negative external reference input 1 (AVSS - 0.3V to AVDD + 0.3V) with analog input 7 function not available on ADS124S06.
32 REFP1/AIN6 input Positive external reference input 1 (AVSS - 0.3V to AVDD + 0.3V) with analog input 6 function not available on ADS124S06.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(5x5)
Category Data Acquisition
Pins 32

CAD (KiCad official)

  • Symbol: ADS124S06IPBSR
  • Footprint: Package_QFP:TQFP-32_5x5mm_P0.5mm
  • 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ads124s06ipbsr-etched.step / ads124s06ipbsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads124s06ipbsr.step / ads124s06ipbsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (115 pp, sha256 62eb7595c22ca2ef, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF