component
ADS1246IPWR
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Texas Instruments Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# ADS1246IPWR++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-16++ADS1246IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DVDD | power_in | Digital power supply voltage (2.7 to 5.25 V); connect 0.1-μF capacitor to DGND. |+| 2 | DGND | power_in | Digital ground reference for digital circuits and serial interface. |+| 3 | CLK | input | External clock input (1 to 4.5 MHz, 25-75% duty cycle); tie to DGND to activate internal oscillator. |+| 4 | RESET | input | Active-low reset input; device held in reset while pin is low, requires 0.6 ms for initialization after rising edge. |+| 5 | REFP | input | Positive external reference input (absolute voltage AVSS-0.1 to AVDD+0.1 V); differential reference voltage 0.5 to (AVDD-AVSS-1) V. |+| 6 | REFN | input | Negative external reference input (absolute voltage AVSS-0.1 to AVDD+0.1 V); negative reference voltage at least 0.5 V below positive reference. |+| 7 | AINP | input | Positive analog input to PGA (absolute voltage AVSS-0.1 to AVDD+0.1 V); differential input range ±VREF/Gain after PGA. |+| 8 | AINN | input | Negative analog input to PGA (absolute voltage AVSS-0.1 to AVDD+0.1 V); input impedance ~5 GΩ nominal. |+| 9 | AVSS | power_in | Negative analog power supply reference (-2.65 to 0.1 V relative to DGND); typically 0 V for unipolar or -2.5 V for bipolar supply. |+| 10 | AVDD | power_in | Positive analog power supply (2.7 to 5.25 V relative to AVSS); connect 0.1-μF capacitor to AVSS for decoupling. |+| 11 | START | input | Conversion start control; pulse high (minimum 3 tCLK) for single conversion or hold high for continuous conversion. |+| 12 | CS | input | Active-low chip select for SPI communication; resets serial interface when taken high; DRDY operation independent of CS. |+| 13 | DRDY | output | Active-low data ready output; transitions low when new 24-bit conversion result is available in output buffer. |+| 14 | DOUT/DRDY | output | Serial data output (MSB first on SCLK rising edge); functions as combined data output/ready when DRDY MODE bit = 1 in ID register (address 0Ah). |+| 15 | DIN | input | Serial data input (SPI mode 1: CPOL=0, CPHA=1); data shifted into device on SCLK falling edge. |+| 16 | SCLK | input | Serial clock input (SPI mode 1: CPOL=0, CPHA=1); minimum period tSCLK = 488 ns; data shifted on falling edges. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `ADS1246IPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `ads1246ipwr-etched.step` / `ads1246ipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1246ipwr.step` / `ads1246ipwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1247) (104 pp, sha256 `08b29c91036dd059`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads1246ipwr-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "ads1246ipwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADC), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads1246ipwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads1246ipwr.kicad_sym",+ "ads1246ipwr.kicad_mod",+ "ads1246ipwr.glb",+ "ads1246ipwr.step",+ "ads1246ipwr.lbr",+ "docs/hero.png",+ "docs/ads1246ipwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADS1246IPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads1247",+ "parts": {+ "symbol": "ads1246ipwr.kicad_sym",+ "footprint": "ads1246ipwr.kicad_mod",+ "model_3d": "ads1246ipwr-etched.glb",+ "model_3d_plain": "ads1246ipwr.glb",+ "model_3d_step": "ads1246ipwr-etched.step",+ "model_3d_step_plain": "ads1246ipwr.step",+ "lbr": "ads1246ipwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C88010"+ },+ "pins": [+ {+ "number": "1",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply voltage (2.7 to 5.25 V); connect 0.1-μF capacitor to DGND."+ },+ {+ "number": "2",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground reference for digital circuits and serial interface."+ },+ {+ "number": "3",+ "name": "CLK",+ "type": "input",+ "description": "External clock input (1 to 4.5 MHz, 25-75% duty cycle); tie to DGND to activate internal oscillator."+ },+ {+ "number": "4",+ "name": "RESET",+ "type": "input",+ "description": "Active-low reset input; device held in reset while pin is low, requires 0.6 ms for initialization after rising edge."+ },+ {+ "number": "5",+ "name": "REFP",+ "type": "input",+ "description": "Positive external reference input (absolute voltage AVSS-0.1 to AVDD+0.1 V); differential reference voltage 0.5 to (AVDD-AVSS-1) V."+ },+ {+ "number": "6",+ "name": "REFN",+ "type": "input",+ "description": "Negative external reference input (absolute voltage AVSS-0.1 to AVDD+0.1 V); negative reference voltage at least 0.5 V below positive reference."+ },+ {+ "number": "7",+ "name": "AINP",+ "type": "input",+ "description": "Positive analog input to PGA (absolute voltage AVSS-0.1 to AVDD+0.1 V); differential input range ±VREF/Gain after PGA."+ },+ {+ "number": "8",+ "name": "AINN",+ "type": "input",+ "description": "Negative analog input to PGA (absolute voltage AVSS-0.1 to AVDD+0.1 V); input impedance ~5 GΩ nominal."+ },+ {+ "number": "9",+ "name": "AVSS",+ "type": "power_in",+ "description": "Negative analog power supply reference (-2.65 to 0.1 V relative to DGND); typically 0 V for unipolar or -2.5 V for bipolar supply."+ },+ {+ "number": "10",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive analog power supply (2.7 to 5.25 V relative to AVSS); connect 0.1-μF capacitor to AVSS for decoupling."+ },+ {+ "number": "11",+ "name": "START",+ "type": "input",+ "description": "Conversion start control; pulse high (minimum 3 tCLK) for single conversion or hold high for continuous conversion."+ },+ {+ "number": "12",+ "name": "CS",+ "type": "input",+ "description": "Active-low chip select for SPI communication; resets serial interface when taken high; DRDY operation independent of CS."+ },+ {+ "number": "13",+ "name": "DRDY",+ "type": "output",+ "description": "Active-low data ready output; transitions low when new 24-bit conversion result is available in output buffer."+ },+ {+ "number": "14",+ "name": "DOUT/DRDY",+ "type": "output",+ "description": "Serial data output (MSB first on SCLK rising edge); functions as combined data output/ready when DRDY MODE bit = 1 in ID register (address 0Ah)."+ },+ {+ "number": "15",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input (SPI mode 1: CPOL=0, CPHA=1); data shifted into device on SCLK falling edge."+ },+ {+ "number": "16",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input (SPI mode 1: CPOL=0, CPHA=1); minimum period tSCLK = 488 ns; data shifted on falling edges."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: DOUT/DRDY pin (pin 14) functions as either serial data output only (DRDY MODE bit = 0) or combined d; External reference is mandatory for ADS1246; differential reference voltage must be 0.5 to (AVDD-AVS; PGA common-mode input voltage requirements (Equation 3: VCM range depends on gain, input signal ampl"+ ],+ "pages_sent": 104,+ "cost_usd": 1.0315,+ "at": "2026-09-23T09:27:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads1247",+ "pages": 104,+ "sha256": "08b29c91036dd059",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}