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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS1246IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-16

ADS1246IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DVDD	power_in	Digital power supply voltage (2.7 to 5.25 V); connect 0.1-μF capacitor to DGND.
2	DGND	power_in	Digital ground reference for digital circuits and serial interface.
3	CLK	input	External clock input (1 to 4.5 MHz, 25-75% duty cycle); tie to DGND to activate internal oscillator.
4	RESET	input	Active-low reset input; device held in reset while pin is low, requires 0.6 ms for initialization after rising edge.
5	REFP	input	Positive external reference input (absolute voltage AVSS-0.1 to AVDD+0.1 V); differential reference voltage 0.5 to (AVDD-AVSS-1) V.
6	REFN	input	Negative external reference input (absolute voltage AVSS-0.1 to AVDD+0.1 V); negative reference voltage at least 0.5 V below positive reference.
7	AINP	input	Positive analog input to PGA (absolute voltage AVSS-0.1 to AVDD+0.1 V); differential input range ±VREF/Gain after PGA.
8	AINN	input	Negative analog input to PGA (absolute voltage AVSS-0.1 to AVDD+0.1 V); input impedance ~5 GΩ nominal.
9	AVSS	power_in	Negative analog power supply reference (-2.65 to 0.1 V relative to DGND); typically 0 V for unipolar or -2.5 V for bipolar supply.
10	AVDD	power_in	Positive analog power supply (2.7 to 5.25 V relative to AVSS); connect 0.1-μF capacitor to AVSS for decoupling.
11	START	input	Conversion start control; pulse high (minimum 3 tCLK) for single conversion or hold high for continuous conversion.
12	CS	input	Active-low chip select for SPI communication; resets serial interface when taken high; DRDY operation independent of CS.
13	DRDY	output	Active-low data ready output; transitions low when new 24-bit conversion result is available in output buffer.
14	DOUT/DRDY	output	Serial data output (MSB first on SCLK rising edge); functions as combined data output/ready when DRDY MODE bit = 1 in ID register (address 0Ah).
15	DIN	input	Serial data input (SPI mode 1: CPOL=0, CPHA=1); data shifted into device on SCLK falling edge.
16	SCLK	input	Serial clock input (SPI mode 1: CPOL=0, CPHA=1); minimum period tSCLK = 488 ns; data shifted on falling edges.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Data Acquisition
Pins	16

CAD (KiCad official)

Symbol: ADS1246IPWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ads1246ipwr-etched.step / ads1246ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1246ipwr.step / ads1246ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (104 pp, sha256 08b29c91036dd059, retrieved 2026-09-23, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF