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Generated by kicad-footprint-generator · KiCad file format 20260206

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docs	Publish 0.1.0 · Ray	17h ago
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ads1242ipwr-etched.glb	ads1242ipwr: factory component page (tier=lcsc) · Ray	17h ago
ads1242ipwr-etched.step	ads1242ipwr: factory component page (tier=lcsc) · Ray	17h ago
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README.md	Initial commit: component/ads1242ipwr · Ray	17h ago

ADS1242IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-16

ADS1242IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Power supply input rated for 2.7V to 5.25V operation.
2	XIN	input	Clock input for external oscillator, maximum 5 MHz.
3	XOUT	output	Clock output for connection to external crystal or ceramic resonator.
4	PDWN	input	Active LOW power down control that disables analog and digital circuits when LOW.
5	VREF+	power_in	Positive differential reference input (0V to VDD); differential voltage (VREF+)−(VREF−) ranges 0.1V to 1.30V (RANGE=0) or 2.6V (RANGE=1).
6	VREF-	power_in	Negative differential reference input (0V to VDD); differential voltage (VREF+)−(VREF−) ranges 0.1V to 1.30V (RANGE=0) or 2.6V (RANGE=1).
7	AIN0/D0	bidirectional	Analog input channel 0 or digital I/O 0, input range GND+0.05V to VDD−1.5V (buffer enabled).
8	AIN1/D1	bidirectional	Analog input channel 1 or digital I/O 1, input range GND+0.05V to VDD−1.5V (buffer enabled).
9	AIN2/D2	bidirectional	Analog input channel 2 or digital I/O 2, input range GND+0.05V to VDD−1.5V (buffer enabled).
10	AIN3/D3	bidirectional	Analog input channel 3 or digital I/O 3, input range GND+0.05V to VDD−1.5V (buffer enabled).
11	GND	power_in	Ground reference.
12	CS	input	Active LOW chip select input for SPI serial interface.
13	DIN	input	Serial data input with Schmitt trigger, 50ns setup time required before SCLK edge.
14	DOUT	tri_state	Serial data output with tri-state (high impedance) when CS is HIGH, valid 50ns after SCLK edge.
15	SCLK	input	Serial clock input with Schmitt trigger, minimum period 4 tOSC or 3 DRDY periods.
16	DRDY	output	Active LOW data ready output indicating when a new conversion result is available.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Data Acquisition
Pins	16

CAD (KiCad official)

Symbol: ADS1242IPWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ads1242ipwr-etched.step / ads1242ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1242ipwr.step / ads1242ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 0bf7c17072b2c943, retrieved 2026-10-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF