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ADS1232IPW

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Texas Instruments Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS1232IPW

Texas Instruments · Analog To Digital Converters (ADCs) · TSSOP-24

ADS1232IPW from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVDD power_in Digital power supply, 2.7 V to 5.3 V; it must be clean and free of glitches and transients.
2 DGND power_in Digital ground.
3 CLKIN/XTAL1 input External crystal connection 1, or external clock input, or tie low to activate the internal oscillator.
4 XTAL2 passive External crystal connection 2.
5 DGND power_in Digital ground.
6 DGND power_in Digital ground.
7 TEMP input Temperature sensor select pin (ADS1232 only); see Table 7-1 for the selection behavior.
8 A0 input Input MUX select pin; see Table 7-1 and Table 7-2 for the channel selection.
9 CAP passive PGA bypass pin; connect a 0.1 µF capacitor across pins 9 and 10.
10 CAP passive PGA bypass pin; connect a 0.1 µF capacitor across pins 9 and 10.
11 AINP1 input Positive analog input, channel 1 (differential pair with AINN1).
12 AINN1 input Negative analog input, channel 1 (differential pair with AINP1).
13 AINN2 input Negative analog input, channel 2 (differential pair with AINP2).
14 AINP2 input Positive analog input, channel 2 (differential pair with AINN2).
15 REFN input Negative reference input.
16 REFP input Positive reference input.
17 AGND power_in Analog ground.
18 AVDD power_in Analog power supply, 2.7 V to 5.3 V.
19 GAIN0 input Gain select pin; see the Low-Noise PGA section for the gain settings.
20 GAIN1 input Gain select pin; see the Low-Noise PGA section for the gain settings.
21 SPEED input Data rate select pin; see the Data Rate section (10 SPS or 80 SPS).
22 PDWN input Power-down pin: hold low to power down and reset the ADC; toggle at device power-up.
23 SCLK input Serial clock: clocks out data on the rising edge; also initiates offset calibration and standby modes.
24 DRDY/DOUT output Dual-purpose output: goes low to indicate valid data ready, and outputs conversion data MSB first on the first rising edge of SCLK.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category ADC/DAC/Data Conversion
Pins 24

CAD (KiCad official)

  • Symbol: ADS1232IPW
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ads1232ipw-etched.step / ads1232ipw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1232ipw.step / ads1232ipw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 00f92c6871a8b92a, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF