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ADS1220IRVAT

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Texas Instruments Analog To Digital Converters (ADC), VQFN-16-EP(3.6x3.6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionads1220irvatfactory-2.0.0extractor-text

Verified ADS1220IRVAT

by Ray · last 7 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

7 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS1220IRVAT · VQFN-16-EP(3.6x3.6) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 78-page datasheet
  • ✓distributor: lcsc C701622, digikey 296-37802-2-ND, mouser 595-ADS1220IRVAT
  • ✓family: Texas_RVA_VQFN-16-1EP_3.5x3.5mm_P0.5mm_EP2.14x2.14mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xorsio9t/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads1220irvat.kicad_sym✓ ads1220irvat.kicad_mod✓ ads1220irvat.step
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Symbol & Footprint

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Contents

README

markdown

ADS1220IRVAT

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-16-EP(3.6x3.6)

ADS1220IRVAT from Texas Instruments, in a VQFN-16-EP(3.6x3.6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input External clock source pin; connect to DGND if not used.
2 DGND power_in Digital ground.
3 AVSS power_in Negative analog power supply.
4 AIN3/REFN1 input Analog input 3 and negative reference input 1; an internal low-side power switch is connected between this pin and AVSS.
5 AIN2 input Analog input 2; absolute voltage limits are AVSS - 0.3 V to AVDD + 0.3 V.
6 REFN0 input Negative reference input 0.
7 REFP0 input Positive reference input 0.
8 AIN1 input Analog input 1; absolute voltage limits are AVSS - 0.3 V to AVDD + 0.3 V.
9 AIN0/REFP1 input Analog input 0 and positive reference input 1; absolute voltage limits are AVSS - 0.3 V to AVDD + 0.3 V.
10 AVDD power_in Positive analog power supply; connect a 100 nF (or larger) capacitor to AVSS.
11 DVDD power_in Positive digital power supply; connect a 100 nF (or larger) capacitor to DGND.
12 DRDY output Data ready, active low; leave unconnected or tie to DVDD using a weak pull-up resistor if not used.
13 DOUT/DRDY output Serial data output combined with data ready; active low.
14 DIN input Serial data input.
15 SCLK input Serial clock input.
16 CS input Chip select, active low; connect to DGND if not used.
17 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3.6x3.6)
Category Data Acquisition
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power-supply voltage AVDD to AVSS -0.3 7 V 5
Power-supply voltage DVDD to DGND -0.3 7 V 5
Power-supply voltage AVSS to DGND -2.8 0.3 V 5
Input current, continuous, any pin except power supply pins -10 10 mA Continuous 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -60 150 °C 5
Unipolar analog power supply AVDD to AVSS 2.3 5.5 V 6
AVSS to DGND (unipolar analog supply) -0.1 0 0.1 V 6
Bipolar analog power supply AVDD to DGND 2.3 2.5 2.75 V 6
Bipolar analog power supply AVSS to DGND -2.75 -2.5 -2.3 V 6
Digital power supply DVDD to DGND 2.3 5.5 V 6
Differential reference input voltage VREF 0.75 2.5 V VREF = VREFPx, VREFNx 6
External clock frequency fCLK 0.5 4.096 4.5 MHz 6
External clock duty cycle 40 60 % 6
Operating ambient temperature TA -40 125 °C 6
Integral nonlinearity INL -15 6 15 ppmFSR Gain = 1 to 128, VCM = 0.5 AVDD, best fit 7
Input offset voltage VIO -4 4 µV PGA disabled, gain = 1 to 4, differential inputs 7
Input offset voltage VIO -30 4 30 µV Gain = 1, differential inputs, TA = 25°C 7
Offset drift 0.08 0.3 µV/°C Gain = 1 to 128, TA = -40°C to +85°C 7
Offset match between any two inputs -20 20 µV Match between any two inputs 7
Gain error -0.1 0.015 0.1 % Gain = 1 to 128, TA = 25°C 7
Gain error -0.015 0.015 % PGA disabled, gain = 1 to 4 7
Gain drift 1 4 ppm/°C Gain = 1 to 128 7
Common-mode rejection ratio CMRR 90 105 dB At dc, gain = 1 7
Common-mode rejection ratio CMRR 95 115 dB fCM = 50Hz, DR = 2000SPS 7
Power-supply rejection ratio PSRR 80 105 dB AVDD at dc, VCM = 0.5 AVDD, gain = 1 7
Power-supply rejection ratio PSRR 100 115 dB DVDD at dc, VCM = 0.5 AVDD, gain = 1 7
Internal voltage reference initial accuracy 2.045 2.048 2.051 V TA = 25°C 7
Reference drift 5 30 ppm/°C 7
Reference input current -10 10 nA REFP0 = VREF, REFN0 = AVSS 7
Internal oscillator accuracy -2 1 2 % Normal mode 7
IDAC accuracy -6 1 6 % All current settings, each IDAC 7
IDAC current match -0.3 0.3 % Between IDACs (not valid for 10µA setting) 7
Temperature sensor accuracy -0.5 0.25 0.5 °C TA = 0°C to +75°C 8
Temperature sensor accuracy -1 0.5 1 °C TA = -40°C to +125°C 8
Temperature sensor accuracy vs analog supply voltage 0.0625 0.25 °C/V 8
Low-side power switch on-resistance RON 3.5 5.5 Ω 8
Input leakage, high IH -10 10 µA VIH = 5.5V 8
Input leakage, low IL -10 10 µA VIL = DGND 8
Analog supply current, power-down mode IAVDD 0.1 3 µA Power-down mode 8
Analog supply current, normal mode, gain = 1 to 16 IAVDD 340 490 µA Normal mode, gain = 1 to 16 8
Digital supply current, power-down mode IDVDD 0.3 5 µA Power-down mode 8
Digital supply current, normal mode IDVDD 75 110 µA Normal mode 8
Power dissipation, normal mode, gain = 1 to 16 PD 1.4 mW Normal mode, gain = 1 to 16 8
Analog supply current, duty-cycle mode, PGA disabled IAVDD 65 µA Duty-cycle mode, PGA disabled 8
Analog supply current, normal mode, PGA disabled IAVDD 240 µA Normal mode, PGA disabled 8
Analog supply current, turbo mode, gain = 1 to 16 IAVDD 540 µA Turbo mode, gain = 1 to 16 8
Digital supply current, duty-cycle mode IDVDD 55 µA Duty-cycle mode 8
Normal-mode rejection ratio, 50Hz NMRR 105 dB 50Hz ±3%, DR = 20SPS, external CLK, 50/60 bit = 10b 7
Normal-mode rejection ratio, 60Hz NMRR 105 dB 60Hz ±3%, DR = 20SPS, external CLK, 50/60 bit = 11b 7
IDAC temperature drift 50 ppm/°C Each IDAC (not valid for 10µA setting) 7
Current through low-side switch 30 mA 8
Thermal resistance, junction-to-ambient RθJA 43.4 °C/W VQFN (RVA), 16 pins 6
Thermal resistance, junction-to-case (top) RθJC(top) 47.3 °C/W VQFN (RVA), 16 pins 6
Thermal resistance, junction-to-board RθJB 18.4 °C/W VQFN (RVA), 16 pins 6
Junction-to-top characterization parameter ψJT 0.6 °C/W VQFN (RVA), 16 pins 6
Junction-to-board characterization parameter ψJB 18.4 °C/W VQFN (RVA), 16 pins 6
Thermal resistance, junction-to-case (bottom) RθJC(bot) 2 °C/W VQFN (RVA), 16 pins 6

CAD (KiCad official)

  • Symbol: ADS1220IRVAT
  • Footprint: Package_DFN_QFN:Texas_RVA_VQFN-16-1EP_3.5x3.5mm_P0.5mm_EP2.14x2.14mm
  • 3D model: VQFN-16-EP(3.6x3.6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ads1220irvat-etched.step / ads1220irvat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1220irvat.step / ads1220irvat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (78 pp, sha256 218e25810febc1d7, retrieved 2026-11-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF