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ADS1220IRVAR

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-16-EP(3.5x3.5)

ADS1220IRVAR from Texas Instruments, in a VQFN-16-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input External clock source input; tie to DGND when unused so the internal oscillator is active, and an external clock must be 0.5 MHz to 4.5 MHz with 40% to 60% duty cycle.
2 DGND power_in Digital ground; DVDD to DGND is rated -0.3 V to 7 V absolute maximum and AVSS to DGND must stay between -2.8 V and 0.3 V.
3 AVSS power_in Negative analog supply; it is 0 V (-0.1 V to 0.1 V) for unipolar operation or -2.75 V to -2.3 V for bipolar operation relative to DGND.
4 AIN3/REFN1 input Analog input 3 and negative reference input 1; it is also tied to AVSS through the internal low-side power switch, so leave it floating when unused.
5 AIN2 input Analog input 2; input voltage must stay between AVSS - 0.3 V and AVDD + 0.3 V to avoid forward-biasing the ESD diodes.
6 REFN0 input Negative reference input 0; it must stay between AVSS - 0.1 V and REFP0 - 0.75 V.
7 REFP0 input Positive reference input 0; it must stay between REFN0 + 0.75 V and AVDD + 0.1 V, with differential reference 0.75 V to AVDD - AVSS.
8 AIN1 input Analog input 1; input voltage must stay between AVSS - 0.3 V and AVDD + 0.3 V to avoid forward-biasing the ESD diodes.
9 AIN0/REFP1 input Analog input 0 and positive reference input 1; input voltage must stay between AVSS - 0.3 V and AVDD + 0.3 V.
10 AVDD power_in Positive analog supply; AVDD to AVSS is rated 7 V absolute maximum and recommended 2.3 V to 5.5 V, with a 100 nF (or larger) capacitor to AVSS.
11 DVDD power_in Positive digital supply; DVDD to DGND is recommended 2.3 V to 5.5 V, with a 100 nF (or larger) capacitor to DGND.
12 DRDY output Data-ready output, active low, indicating a new conversion result is available; if unused, leave it unconnected or pull it up to DVDD through a weak pull-up resistor.
13 DOUT/DRDY output Serial data output combined with data-ready signal, active low; it goes high impedance when CS is high and can be configured via DRDYM to indicate data ready.
14 DIN input Serial data input latched on the falling edge of SCLK for commands and register data; the device never drives this pin.
15 SCLK input Serial clock input with Schmitt-trigger; it must be kept low when the serial interface is idle and kept clean to avoid spurious data shifts.
16 CS input Chip select, active low; when CS is taken high the serial interface resets and DOUT/DRDY goes high impedance, and CS may be tied to DGND if the bus is not shared.
17 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3.5x3.5)
Category Data Acquisition
Pins 17

CAD (KiCad official)

  • Symbol: ADS1220IRVAR
  • Footprint: Package_DFN_QFN:Texas_RVA_VQFN-16-1EP_3.5x3.5mm_P0.5mm_EP2.14x2.14mm
  • 3D model: VQFN-16-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (80 pp, sha256 b6715c9f35b93db7, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF