# ADS1202IPWT

**Texas Instruments** · ADC/DAC - Specialized · TSSOP-8

ADS1202IPWT from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | M0 | input | Mode input that, together with M1, selects the serial interface mode; digital input is TTL with Schmitt trigger, VIH 2.6V min, VIL 0.8V max. |
| 2 | VIN+ | power_in | Noninverting analog input with ±250mV input range (±320mV full-scale) and common-mode range of -0.1V to 5V. |
| 3 | VIN- | power_in | Inverting analog input with ±250mV input range (±320mV full-scale) and common-mode range of -0.1V to 5V. |
| 4 | M1 | input | Mode input that, together with M0, selects the serial interface mode; digital input is TTL with Schmitt trigger, VIH 2.6V min, VIL 0.8V max. |
| 5 | GND | power_in | Power supply ground. |
| 6 | MDAT | output | Modulator data output with 30pF max load capacitance and VOL 0.4V max at 5mA. |
| 7 | MCLK | bidirectional | Modulator clock input or output; internal clock 8 to 12MHz in modes 0, 1, 2 and external clock 16 to 24MHz in mode 3. |
| 8 | VDD | power_in | Power supply, +5V nominal (4.75V to 5.25V recommended, absolute maximum 6V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Data Converters |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Nonlinearity | INL |  | 3 | 12 | LSB |  | 3 |
| Integral Nonlinearity | INL |  | 0.005 | 0.018 | % |  | 3 |
| Input Offset | VOS | -1000 | 300 | 1000 | µV |  | 3 |
| Gain Error | GERR | -2 | 0.25 | 2 | % |  | 3 |
| Operating Common-Mode Signal |  | -0.1 |  | 5 | V |  | 3 |
| Reference Voltage | VOUT | 2.45 | 2.5 | 2.55 | V | Scale to 320mV | 3 |
| Reference Accuracy |  | -2 |  | 2 | % | Scale to 320mV | 3 |
| Internal Clock Frequency (Modes 0, 1, 2) |  | 8 | 10 | 12 | MHz |  | 3 |
| External Clock Frequency (Mode 3) |  | 16 | 20 | 24 | MHz |  | 3 |
| Signal-to-Noise Ratio | SNR | 67 | 70.5 |  | dB | VIN = ±250mVp-p at 5kHz | 3 |
| High-Level Input Voltage | VIH | 2.6 |  |  | V |  | 3 |
| Low-Level Input Voltage | VIL | -0.3 |  | 0.8 | V |  | 3 |
| High-Level Input Current | IIH |  | 0.005 | 2.5 | µA | VI = VDD | 3 |
| Low-Level Input Current | IIL | -2.5 | 0.005 |  | µA | VI = GND | 3 |
| High-Level Digital Output | VOH | 4.6 |  |  | V | VDD = 4.5V, IO = -5mA | 3 |
| High-Level Digital Output | VOH | 3.9 |  |  | V | VDD = 4.5V, IO = -15mA | 3 |
| Low-Level Digital Output | VOL |  |  | 0.4 | V | VDD = 4.5V, IO = 5mA | 3 |
| Low-Level Digital Output | VOL |  |  | 1.1 | V | VDD = 4.5V, IO = 15mA | 3 |
| Supply Voltage | VDD | 4.5 | 5 | 5.5 | V |  | 3 |
| Operating Supply Current | ICC |  | 8 | 9.5 | mA | Mode 0 | 3 |
| Operating Supply Current | ICC |  | 6 | 7.5 | mA | Mode 3 | 3 |
| Power Dissipation |  |  | 40 | 47.5 | mW | VDD = 5V, Mode 0 | 3 |
| Power Dissipation |  |  | 30 | 37.5 | mW | VDD = 5V, Mode 3 | 3 |
| Operating Temperature |  | -40 |  | 85 | °C |  | 3 |
| Supply Voltage | VDD | 4.75 | 5 | 5.25 | V |  | 2 |
| Analog Input Voltage | VIN | -250 |  | 250 | mV |  | 2 |
| Operating Common-Mode Signal | VCM | 0 |  | 5 | V |  | 2 |
| External Clock |  | 16 | 20 | 24 | MHz |  | 2 |
| Operating Junction Temperature Range |  | -40 |  | 105 | °C |  | 2 |
| Supply Voltage, GND to VDD |  | -0.3 |  | 6 | V |  | 2 |
| Power Dissipation |  |  |  | 0.25 | W |  | 2 |
| Operating Virtual Junction Temperature Range | TJ | -40 |  | 150 | °C |  | 2 |
| Operating Free-Air Temperature Range | TA | -40 |  | 85 | °C |  | 2 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 2 |
| Lead Temperature |  |  |  | 260 | °C | 1.6mm (1/16") from case for 10s | 2 |
| Clock Period | tC1 | 83 |  | 125 | ns | Mode 0 | 5 |
| Data delay after falling edge of clock | tD1 | -2 |  | 2 | ns | Mode 0 | 5 |
| Clock Period | tC2 | 166 |  | 250 | ns | Mode 1 | 5 |
| Data delay after rising edge of clock | tD2 | -2 |  | 2 | ns | Mode 1 | 5 |
| Clock Period | tC4 | 41 |  | 62 | ns | Mode 3 | 5 |
| Clock HIGH Time | tW4 | 10 |  |  | ns | Mode 3 | 5 |
| Data delay after falling edge of clock | tD4 | 0 |  | 10 | ns | Mode 3 | 5 |
| Rise Time of Clock | tR1 | 0 |  | 10 | ns | Mode 3 | 5 |
| Fall Time of Clock | tF1 | 0 |  | 10 | ns | Mode 3 | 5 |
| Differential Linearity | DNL |  | 1 |  | LSB |  | 3 |
| Input Offset Drift | TCVOS |  | 28 |  | µV/°C |  | 3 |
| Gain Error Drift | TCGERR |  | 20 |  | ppm/°C |  | 3 |
| Reference Temperature Drift | dVOUT/dT |  | 20 |  | ppm/°C |  | 3 |
| Signal-to-Noise Ratio + Distortion | SINAD |  | 70 |  | dB | VIN = ±250mVp-p at 5kHz | 3 |

## CAD (KiCad official)

- Symbol: `ADS1202IPWT`
- Footprint: `Package_SO:TSSOP-8_4.4x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `ads1202ipwt-etched.step` / `ads1202ipwt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1202ipwt.step` / `ads1202ipwt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ads1202ipwt.pdf) (27 pp, sha256 `4a3da25c3802e2ba`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ads1202ipwt-datasheet.pdf)