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ADS1198CPAG

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Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADS1198CPAG

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1198CPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Differential analog negative input 8 (ADS1198 only); connect unused analog inputs to AVDD.
2 IN8P input Differential analog positive input 8 (ADS1198 only); connect unused analog inputs to AVDD.
3 IN7N input Differential analog negative input 7 (ADS1198 only); connect unused analog inputs to AVDD.
4 IN7P input Differential analog positive input 7 (ADS1198 only); connect unused analog inputs to AVDD.
5 IN6N input Differential analog negative input 6 (ADS1196/8 only); connect unused analog inputs to AVDD.
6 IN6P input Differential analog positive input 6 (ADS1196/8 only); connect unused analog inputs to AVDD.
7 IN5N input Differential analog negative input 5 (ADS1196/8 only); connect unused analog inputs to AVDD.
8 IN5P input Differential analog positive input 5 (ADS1196/8 only); connect unused analog inputs to AVDD.
9 IN4N input Differential analog negative input 4; connect unused analog inputs to AVDD.
10 IN4P input Differential analog positive input 4; connect unused analog inputs to AVDD.
11 IN3N input Differential analog negative input 3; connect unused analog inputs to AVDD.
12 IN3P input Differential analog positive input 3; connect unused analog inputs to AVDD.
13 IN2N input Differential analog negative input 2; connect unused analog inputs to AVDD.
14 IN2P input Differential analog positive input 2; connect unused analog inputs to AVDD.
15 IN1N input Differential analog negative input 1; connect unused analog inputs to AVDD.
16 IN1P input Differential analog positive input 1; connect unused analog inputs to AVDD.
17 TESTP_PACE_OUT1 bidirectional Internal test signal or single-ended buffer output based on register settings; short to AVDD if unused.
18 TESTN_PACE_OUT2 bidirectional Internal test signal or single-ended buffer output based on register settings; short to AVDD if unused.
19 AVDD power_in Analog supply; AVDD to AVSS is specified at -0.3 to +5.5 V absolute maximum, and the analog supply is 2.7 V to 5.25 V.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog supply; AVDD to AVSS is specified at -0.3 to +5.5 V absolute maximum.
22 AVDD power_in Analog supply; AVDD to AVSS is specified at -0.3 to +5.5 V absolute maximum.
23 AVSS power_in Analog ground.
24 VREFP bidirectional Positive reference voltage; VREF input is limited to AVSS - 0.3 V to AVDD + 0.3 V.
25 VREFN input Negative reference voltage; VREF input is limited to AVSS - 0.3 V to AVDD + 0.3 V.
26 VCAP4 output Analog bypass capacitor connection.
27 NC unconnected No connection; leave floating.
28 VCAP1 passive Analog bypass capacitor connection.
29 NC unconnected No connection; leave floating.
30 VCAP2 passive Analog bypass capacitor connection.
31 RESV1 input Reserved for future use; must tie to logic low (DGND).
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input SPI data input.
35 PWDN input Power-down; active low.
36 RESET input System reset; active low.
37 CLK bidirectional External master clock input or internal clock output.
38 START input Start conversion.
39 CS input SPI chip select; active low.
40 SCLK input SPI clock.
41 DAISY_IN input Daisy-chain input; if not used, short to logic zero (DGND).
42 GPIO1 bidirectional General-purpose input/output pin.
43 DOUT output SPI data output; the device is specified at DVDD 1.65 V to 3.6 V.
44 GPIO2 bidirectional General-purpose input/output pin.
45 GPIO3 bidirectional General-purpose input/output pin.
46 GPIO4 bidirectional General-purpose input/output pin.
47 DRDY output Data ready; active low.
48 DVDD power_in Digital power supply; DVDD to DGND is specified at -0.3 to +3.9 V absolute maximum.
49 DGND power_in Digital ground.
50 DVDD power_in Digital power supply; DVDD to DGND is specified at -0.3 to +3.9 V absolute maximum.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select.
53 AVSS1 power_in Analog ground for the charge pump.
54 AVDD1 power_in Analog supply for the charge pump.
55 VCAP3 power_out Analog bypass capacitor; internally generated AVDD + 1.9 V.
56 AVDD power_in Analog supply.
57 AVSS power_in Analog ground.
58 AVSS power_in Analog ground for the charge pump.
59 AVDD power_in Analog supply for the charge pump.
60 RLDREF input Right leg drive noninverting input.
61 RLDINV bidirectional Right leg drive inverting input.
62 RLDIN input Right leg drive input to the MUX; if unused, short to AVDD.
63 RLDOUT output Right leg drive output.
64 WCT output Wilson Center Terminal output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS1198CPAG
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads1198cpag-etched.step / ads1198cpag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1198cpag.step / ads1198cpag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (81 pp, sha256 3923a51be1b79af3, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF