component
ADS1194CPAGR
Public Made by Adomby adom
Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# ADS1194CPAGR++**Texas Instruments** · Analog Front End (AFE) · TQFP-64(10x10)++ADS1194CPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN8N | input | Differential analog negative input 8 (ADS1198 only); connect unused inputs to AVDD. |+| 2 | IN8P | input | Differential analog positive input 8 (ADS1198 only); connect unused inputs to AVDD. |+| 3 | IN7N | input | Differential analog negative input 7 (ADS1198 only); connect unused inputs to AVDD. |+| 4 | IN7P | input | Differential analog positive input 7 (ADS1198 only); connect unused inputs to AVDD. |+| 5 | IN6N | input | Differential analog negative input 6 (ADS1196/8 only); connect unused inputs to AVDD. |+| 6 | IN6P | input | Differential analog positive input 6 (ADS1196/8 only); connect unused inputs to AVDD. |+| 7 | IN5N | input | Differential analog negative input 5 (ADS1196/8 only); connect unused inputs to AVDD. |+| 8 | IN5P | input | Differential analog positive input 5 (ADS1196/8 only); connect unused inputs to AVDD. |+| 9 | IN4N | input | Differential analog negative input 4; connect unused inputs to AVDD. |+| 10 | IN4P | input | Differential analog positive input 4; connect unused inputs to AVDD. |+| 11 | IN3N | input | Differential analog negative input 3; connect unused inputs to AVDD. |+| 12 | IN3P | input | Differential analog positive input 3; connect unused inputs to AVDD. |+| 13 | IN2N | input | Differential analog negative input 2; connect unused inputs to AVDD. |+| 14 | IN2P | input | Differential analog positive input 2; connect unused inputs to AVDD. |+| 15 | IN1N | input | Differential analog negative input 1; connect unused inputs to AVDD. |+| 16 | IN1P | input | Differential analog positive input 1; connect unused inputs to AVDD. |+| 17 | TESTP_PACE_OUT1 | bidirectional | Internal test signal or pace detection output based on register settings; short to AVDD if unused. |+| 18 | TESTN_PACE_OUT2 | bidirectional | Internal test signal or pace detection output based on register settings; short to AVDD if unused. |+| 19 | AVDD | power_in | Analog supply voltage, 2.7V to 5.25V. |+| 20 | AVSS | power_in | Analog ground, reference for analog supply. |+| 21 | AVDD | power_in | Analog supply voltage, 2.7V to 5.25V. |+| 22 | AVDD | power_in | Analog supply voltage, 2.7V to 5.25V. |+| 23 | AVSS | power_in | Analog ground, reference for analog supply. |+| 24 | VREFP | bidirectional | Positive reference voltage, 2.5V for 3V supply or 4.1V for 5V supply; internally generated as 2.4V or 4.0V. |+| 25 | VREFN | input | Negative reference voltage, typically connected to AVSS for internal reference mode. |+| 26 | VCAP4 | passive | Analog supply bypass capacitor; connect to AVSS with 10µF and 0.1µF capacitors placed as close to package as possible. |+| 27 | NC | unconnected | No connection; leave floating. |+| 28 | VCAP1 | passive | Analog supply bypass capacitor; connect to AVSS with 10µF and 0.1µF capacitors placed as close to package as possible. |+| 29 | NC | unconnected | No connection; leave floating. |+| 30 | VCAP2 | passive | Analog supply bypass capacitor; connect to AVSS with 1µF and 0.1µF capacitors placed as close to package as possible. |+| 31 | RESV1 | input | Reserved for future use; must tie to logic low (DGND). |+| 32 | AVSS | power_in | Analog ground, reference for analog supply. |+| 33 | DGND | power_in | Digital ground, reference for digital supply. |+| 34 | DIN | input | SPI serial data input; device latches data on falling edge of SCLK. |+| 35 | PWDN | input | Power-down active-low input; pull low to enter low-power power-down mode. |+| 36 | RESET | input | System reset active-low input; apply minimum 2 tCLK low pulse to reset device. |+| 37 | CLK | bidirectional | External master clock input when CLKSEL=0 or internal clock output when CLKSEL=1 and CLK_EN=1; maximum 2.25MHz for external. |+| 38 | START | input | Start conversion input; must be held high for at least 2 tCLK cycles to begin conversions. |+| 39 | CS | input | SPI chip select active-low input; must remain low for entire duration of serial communication. |+| 40 | SCLK | input | SPI serial clock input; maximum frequency 16MHz at DVDD=3.6V or 8MHz at DVDD=1.65V. |+| 41 | DAISY_IN | input | Daisy-chain input; tie to DGND (logic zero) if daisy-chain mode not used. |+| 42 | GPIO1 | bidirectional | General-purpose input/output pin; individually configurable as input or output, can be used as PACEIN signal. |+| 43 | DOUT | output | SPI serial data output; data shift out on rising edge of SCLK, goes to high-impedance when CS is high. |+| 44 | GPIO2 | bidirectional | General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP_BLK signal. |+| 45 | GPIO3 | bidirectional | General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP signal. |+| 46 | GPIO4 | bidirectional | General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP_PH signal. |+| 47 | DRDY | output | Data ready active-low output; transitions low when new conversion data are available. |+| 48 | DVDD | power_in | Digital supply voltage, 1.65V to 3.6V. |+| 49 | DGND | power_in | Digital ground, reference for digital supply. |+| 50 | DVDD | power_in | Digital supply voltage, 1.65V to 3.6V. |+| 51 | DGND | power_in | Digital ground, reference for digital supply. |+| 52 | CLKSEL | input | Master clock select input; connect to DVDD for internal oscillator or DGND for external clock source. |+| 53 | AVSS1 | power_in | Analog ground for charge pump; star-connect to AVSS and AVDD for optimal performance. |+| 54 | AVDD1 | power_in | Analog supply for charge pump; star-connect to AVDD and AVSS for optimal performance. |+| 55 | VCAP3 | passive | Bypass capacitor for internally-generated AVDD+1.9V; connect to AVSS with 1µF capacitor placed as close to package as possible. |+| 56 | AVDD | power_in | Analog supply voltage, 2.7V to 5.25V. |+| 57 | AVSS | power_in | Analog ground, reference for analog supply. |+| 58 | AVSS | power_in | Analog ground for charge pump; star-connect to AVSS1. |+| 59 | AVDD | power_in | Analog supply for charge pump; star-connect to AVDD1. |+| 60 | RLDREF | input | Right leg drive noninverting input; connect to (AVDD+AVSS)/2 externally or set RLDREF_INT for internal generation. |+| 61 | RLDINV | bidirectional | Right leg drive inverting input; part of RLD amplifier feedback loop for common-mode rejection. |+| 62 | RLDIN | input | Right leg drive input to multiplexer; can route RLD signal to electrode or short to AVDD if unused. |+| 63 | RLDOUT | output | Right leg drive output; provides inverted common-mode feedback signal to electrodes for reducing interference. |+| 64 | WCT | output | Wilson Center Terminal output; low-current (50µA max) buffered average of selected ECG leads. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-64(10x10) |+| Category | Data Acquisition |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `ADS1194CPAGR`+- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`+- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `ads1194cpagr-etched.step` / `ads1194cpagr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1194cpagr.step` / `ads1194cpagr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1194) (81 pp, sha256 `3923a51be1b79af3`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads1194cpagr-datasheet.pdf)
page.jsonadded+479@@ -0,0 +1,479 @@+{+ "slug": "ads1194cpagr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads1194cpagr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads1194cpagr.kicad_sym",+ "ads1194cpagr.kicad_mod",+ "ads1194cpagr.glb",+ "ads1194cpagr.step",+ "ads1194cpagr.lbr",+ "docs/hero.png",+ "docs/ads1194cpagr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADS1194CPAGR",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-64(10x10)",+ "pin_count": 64,+ "category": "Data Acquisition",+ "subcategory": "Analog Front End (AFE)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads1194",+ "parts": {+ "symbol": "ads1194cpagr.kicad_sym",+ "footprint": "ads1194cpagr.kicad_mod",+ "model_3d": "ads1194cpagr-etched.glb",+ "model_3d_plain": "ads1194cpagr.glb",+ "model_3d_step": "ads1194cpagr-etched.step",+ "model_3d_step_plain": "ads1194cpagr.step",+ "lbr": "ads1194cpagr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2864654"+ },+ "pins": [+ {+ "number": "1",+ "name": "IN8N",+ "type": "input",+ "description": "Differential analog negative input 8 (ADS1198 only); connect unused inputs to AVDD."+ },+ {+ "number": "2",+ "name": "IN8P",+ "type": "input",+ "description": "Differential analog positive input 8 (ADS1198 only); connect unused inputs to AVDD."+ },+ {+ "number": "3",+ "name": "IN7N",+ "type": "input",+ "description": "Differential analog negative input 7 (ADS1198 only); connect unused inputs to AVDD."+ },+ {+ "number": "4",+ "name": "IN7P",+ "type": "input",+ "description": "Differential analog positive input 7 (ADS1198 only); connect unused inputs to AVDD."+ },+ {+ "number": "5",+ "name": "IN6N",+ "type": "input",+ "description": "Differential analog negative input 6 (ADS1196/8 only); connect unused inputs to AVDD."+ },+ {+ "number": "6",+ "name": "IN6P",+ "type": "input",+ "description": "Differential analog positive input 6 (ADS1196/8 only); connect unused inputs to AVDD."+ },+ {+ "number": "7",+ "name": "IN5N",+ "type": "input",+ "description": "Differential analog negative input 5 (ADS1196/8 only); connect unused inputs to AVDD."+ },+ {+ "number": "8",+ "name": "IN5P",+ "type": "input",+ "description": "Differential analog positive input 5 (ADS1196/8 only); connect unused inputs to AVDD."+ },+ {+ "number": "9",+ "name": "IN4N",+ "type": "input",+ "description": "Differential analog negative input 4; connect unused inputs to AVDD."+ },+ {+ "number": "10",+ "name": "IN4P",+ "type": "input",+ "description": "Differential analog positive input 4; connect unused inputs to AVDD."+ },+ {+ "number": "11",+ "name": "IN3N",+ "type": "input",+ "description": "Differential analog negative input 3; connect unused inputs to AVDD."+ },+ {+ "number": "12",+ "name": "IN3P",+ "type": "input",+ "description": "Differential analog positive input 3; connect unused inputs to AVDD."+ },+ {+ "number": "13",+ "name": "IN2N",+ "type": "input",+ "description": "Differential analog negative input 2; connect unused inputs to AVDD."+ },+ {+ "number": "14",+ "name": "IN2P",+ "type": "input",+ "description": "Differential analog positive input 2; connect unused inputs to AVDD."+ },+ {+ "number": "15",+ "name": "IN1N",+ "type": "input",+ "description": "Differential analog negative input 1; connect unused inputs to AVDD."+ },+ {+ "number": "16",+ "name": "IN1P",+ "type": "input",+ "description": "Differential analog positive input 1; connect unused inputs to AVDD."+ },+ {+ "number": "17",+ "name": "TESTP_PACE_OUT1",+ "type": "bidirectional",+ "description": "Internal test signal or pace detection output based on register settings; short to AVDD if unused."+ },+ {+ "number": "18",+ "name": "TESTN_PACE_OUT2",+ "type": "bidirectional",+ "description": "Internal test signal or pace detection output based on register settings; short to AVDD if unused."+ },+ {+ "number": "19",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage, 2.7V to 5.25V."+ },+ {+ "number": "20",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, reference for analog supply."+ },+ {+ "number": "21",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage, 2.7V to 5.25V."+ },+ {+ "number": "22",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage, 2.7V to 5.25V."+ },+ {+ "number": "23",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, reference for analog supply."+ },+ {+ "number": "24",+ "name": "VREFP",+ "type": "bidirectional",+ "description": "Positive reference voltage, 2.5V for 3V supply or 4.1V for 5V supply; internally generated as 2.4V or 4.0V."+ },+ {+ "number": "25",+ "name": "VREFN",+ "type": "input",+ "description": "Negative reference voltage, typically connected to AVSS for internal reference mode."+ },+ {+ "number": "26",+ "name": "VCAP4",+ "type": "passive",+ "description": "Analog supply bypass capacitor; connect to AVSS with 10µF and 0.1µF capacitors placed as close to package as possible."+ },+ {+ "number": "27",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave floating."+ },+ {+ "number": "28",+ "name": "VCAP1",+ "type": "passive",+ "description": "Analog supply bypass capacitor; connect to AVSS with 10µF and 0.1µF capacitors placed as close to package as possible."+ },+ {+ "number": "29",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave floating."+ },+ {+ "number": "30",+ "name": "VCAP2",+ "type": "passive",+ "description": "Analog supply bypass capacitor; connect to AVSS with 1µF and 0.1µF capacitors placed as close to package as possible."+ },+ {+ "number": "31",+ "name": "RESV1",+ "type": "input",+ "description": "Reserved for future use; must tie to logic low (DGND)."+ },+ {+ "number": "32",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, reference for analog supply."+ },+ {+ "number": "33",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground, reference for digital supply."+ },+ {+ "number": "34",+ "name": "DIN",+ "type": "input",+ "description": "SPI serial data input; device latches data on falling edge of SCLK."+ },+ {+ "number": "35",+ "name": "PWDN",+ "type": "input",+ "description": "Power-down active-low input; pull low to enter low-power power-down mode."+ },+ {+ "number": "36",+ "name": "RESET",+ "type": "input",+ "description": "System reset active-low input; apply minimum 2 tCLK low pulse to reset device."+ },+ {+ "number": "37",+ "name": "CLK",+ "type": "bidirectional",+ "description": "External master clock input when CLKSEL=0 or internal clock output when CLKSEL=1 and CLK_EN=1; maximum 2.25MHz for external."+ },+ {+ "number": "38",+ "name": "START",+ "type": "input",+ "description": "Start conversion input; must be held high for at least 2 tCLK cycles to begin conversions."+ },+ {+ "number": "39",+ "name": "CS",+ "type": "input",+ "description": "SPI chip select active-low input; must remain low for entire duration of serial communication."+ },+ {+ "number": "40",+ "name": "SCLK",+ "type": "input",+ "description": "SPI serial clock input; maximum frequency 16MHz at DVDD=3.6V or 8MHz at DVDD=1.65V."+ },+ {+ "number": "41",+ "name": "DAISY_IN",+ "type": "input",+ "description": "Daisy-chain input; tie to DGND (logic zero) if daisy-chain mode not used."+ },+ {+ "number": "42",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose input/output pin; individually configurable as input or output, can be used as PACEIN signal."+ },+ {+ "number": "43",+ "name": "DOUT",+ "type": "output",+ "description": "SPI serial data output; data shift out on rising edge of SCLK, goes to high-impedance when CS is high."+ },+ {+ "number": "44",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP_BLK signal."+ },+ {+ "number": "45",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP signal."+ },+ {+ "number": "46",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP_PH signal."+ },+ {+ "number": "47",+ "name": "DRDY",+ "type": "output",+ "description": "Data ready active-low output; transitions low when new conversion data are available."+ },+ {+ "number": "48",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply voltage, 1.65V to 3.6V."+ },+ {+ "number": "49",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground, reference for digital supply."+ },+ {+ "number": "50",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply voltage, 1.65V to 3.6V."+ },+ {+ "number": "51",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground, reference for digital supply."+ },+ {+ "number": "52",+ "name": "CLKSEL",+ "type": "input",+ "description": "Master clock select input; connect to DVDD for internal oscillator or DGND for external clock source."+ },+ {+ "number": "53",+ "name": "AVSS1",+ "type": "power_in",+ "description": "Analog ground for charge pump; star-connect to AVSS and AVDD for optimal performance."+ },+ {+ "number": "54",+ "name": "AVDD1",+ "type": "power_in",+ "description": "Analog supply for charge pump; star-connect to AVDD and AVSS for optimal performance."+ },+ {+ "number": "55",+ "name": "VCAP3",+ "type": "passive",+ "description": "Bypass capacitor for internally-generated AVDD+1.9V; connect to AVSS with 1µF capacitor placed as close to package as possible."+ },+ {+ "number": "56",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage, 2.7V to 5.25V."+ },+ {+ "number": "57",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, reference for analog supply."+ },+ {+ "number": "58",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground for charge pump; star-connect to AVSS1."+ },+ {+ "number": "59",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply for charge pump; star-connect to AVDD1."+ },+ {+ "number": "60",+ "name": "RLDREF",+ "type": "input",+ "description": "Right leg drive noninverting input; connect to (AVDD+AVSS)/2 externally or set RLDREF_INT for internal generation."+ },+ {+ "number": "61",+ "name": "RLDINV",+ "type": "bidirectional",+ "description": "Right leg drive inverting input; part of RLD amplifier feedback loop for common-mode rejection."+ },+ {+ "number": "62",+ "name": "RLDIN",+ "type": "input",+ "description": "Right leg drive input to multiplexer; can route RLD signal to electrode or short to AVDD if unused."+ },+ {+ "number": "63",+ "name": "RLDOUT",+ "type": "output",+ "description": "Right leg drive output; provides inverted common-mode feedback signal to electrodes for reducing interference."+ },+ {+ "number": "64",+ "name": "WCT",+ "type": "output",+ "description": "Wilson Center Terminal output; low-current (50µA max) buffered average of selected ECG leads."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: ADS1194 is a 4-channel variant; pins IN5-IN8 (channels 5-8) are present on package but not used by t"+ ],+ "pages_sent": 81,+ "cost_usd": 1.0573,+ "at": "2026-09-17T22:13:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads1194",+ "pages": 81,+ "sha256": "3923a51be1b79af3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}