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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS1194CPAGR

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1194CPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN8N	input	Differential analog negative input 8 (ADS1198 only); connect unused inputs to AVDD.
2	IN8P	input	Differential analog positive input 8 (ADS1198 only); connect unused inputs to AVDD.
3	IN7N	input	Differential analog negative input 7 (ADS1198 only); connect unused inputs to AVDD.
4	IN7P	input	Differential analog positive input 7 (ADS1198 only); connect unused inputs to AVDD.
5	IN6N	input	Differential analog negative input 6 (ADS1196/8 only); connect unused inputs to AVDD.
6	IN6P	input	Differential analog positive input 6 (ADS1196/8 only); connect unused inputs to AVDD.
7	IN5N	input	Differential analog negative input 5 (ADS1196/8 only); connect unused inputs to AVDD.
8	IN5P	input	Differential analog positive input 5 (ADS1196/8 only); connect unused inputs to AVDD.
9	IN4N	input	Differential analog negative input 4; connect unused inputs to AVDD.
10	IN4P	input	Differential analog positive input 4; connect unused inputs to AVDD.
11	IN3N	input	Differential analog negative input 3; connect unused inputs to AVDD.
12	IN3P	input	Differential analog positive input 3; connect unused inputs to AVDD.
13	IN2N	input	Differential analog negative input 2; connect unused inputs to AVDD.
14	IN2P	input	Differential analog positive input 2; connect unused inputs to AVDD.
15	IN1N	input	Differential analog negative input 1; connect unused inputs to AVDD.
16	IN1P	input	Differential analog positive input 1; connect unused inputs to AVDD.
17	TESTP_PACE_OUT1	bidirectional	Internal test signal or pace detection output based on register settings; short to AVDD if unused.
18	TESTN_PACE_OUT2	bidirectional	Internal test signal or pace detection output based on register settings; short to AVDD if unused.
19	AVDD	power_in	Analog supply voltage, 2.7V to 5.25V.
20	AVSS	power_in	Analog ground, reference for analog supply.
21	AVDD	power_in	Analog supply voltage, 2.7V to 5.25V.
22	AVDD	power_in	Analog supply voltage, 2.7V to 5.25V.
23	AVSS	power_in	Analog ground, reference for analog supply.
24	VREFP	bidirectional	Positive reference voltage, 2.5V for 3V supply or 4.1V for 5V supply; internally generated as 2.4V or 4.0V.
25	VREFN	input	Negative reference voltage, typically connected to AVSS for internal reference mode.
26	VCAP4	passive	Analog supply bypass capacitor; connect to AVSS with 10µF and 0.1µF capacitors placed as close to package as possible.
27	NC	unconnected	No connection; leave floating.
28	VCAP1	passive	Analog supply bypass capacitor; connect to AVSS with 10µF and 0.1µF capacitors placed as close to package as possible.
29	NC	unconnected	No connection; leave floating.
30	VCAP2	passive	Analog supply bypass capacitor; connect to AVSS with 1µF and 0.1µF capacitors placed as close to package as possible.
31	RESV1	input	Reserved for future use; must tie to logic low (DGND).
32	AVSS	power_in	Analog ground, reference for analog supply.
33	DGND	power_in	Digital ground, reference for digital supply.
34	DIN	input	SPI serial data input; device latches data on falling edge of SCLK.
35	PWDN	input	Power-down active-low input; pull low to enter low-power power-down mode.
36	RESET	input	System reset active-low input; apply minimum 2 tCLK low pulse to reset device.
37	CLK	bidirectional	External master clock input when CLKSEL=0 or internal clock output when CLKSEL=1 and CLK_EN=1; maximum 2.25MHz for external.
38	START	input	Start conversion input; must be held high for at least 2 tCLK cycles to begin conversions.
39	CS	input	SPI chip select active-low input; must remain low for entire duration of serial communication.
40	SCLK	input	SPI serial clock input; maximum frequency 16MHz at DVDD=3.6V or 8MHz at DVDD=1.65V.
41	DAISY_IN	input	Daisy-chain input; tie to DGND (logic zero) if daisy-chain mode not used.
42	GPIO1	bidirectional	General-purpose input/output pin; individually configurable as input or output, can be used as PACEIN signal.
43	DOUT	output	SPI serial data output; data shift out on rising edge of SCLK, goes to high-impedance when CS is high.
44	GPIO2	bidirectional	General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP_BLK signal.
45	GPIO3	bidirectional	General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP signal.
46	GPIO4	bidirectional	General-purpose input/output pin; individually configurable as input or output, multiplexed with RESP_PH signal.
47	DRDY	output	Data ready active-low output; transitions low when new conversion data are available.
48	DVDD	power_in	Digital supply voltage, 1.65V to 3.6V.
49	DGND	power_in	Digital ground, reference for digital supply.
50	DVDD	power_in	Digital supply voltage, 1.65V to 3.6V.
51	DGND	power_in	Digital ground, reference for digital supply.
52	CLKSEL	input	Master clock select input; connect to DVDD for internal oscillator or DGND for external clock source.
53	AVSS1	power_in	Analog ground for charge pump; star-connect to AVSS and AVDD for optimal performance.
54	AVDD1	power_in	Analog supply for charge pump; star-connect to AVDD and AVSS for optimal performance.
55	VCAP3	passive	Bypass capacitor for internally-generated AVDD+1.9V; connect to AVSS with 1µF capacitor placed as close to package as possible.
56	AVDD	power_in	Analog supply voltage, 2.7V to 5.25V.
57	AVSS	power_in	Analog ground, reference for analog supply.
58	AVSS	power_in	Analog ground for charge pump; star-connect to AVSS1.
59	AVDD	power_in	Analog supply for charge pump; star-connect to AVDD1.
60	RLDREF	input	Right leg drive noninverting input; connect to (AVDD+AVSS)/2 externally or set RLDREF_INT for internal generation.
61	RLDINV	bidirectional	Right leg drive inverting input; part of RLD amplifier feedback loop for common-mode rejection.
62	RLDIN	input	Right leg drive input to multiplexer; can route RLD signal to electrode or short to AVDD if unused.
63	RLDOUT	output	Right leg drive output; provides inverted common-mode feedback signal to electrodes for reducing interference.
64	WCT	output	Wilson Center Terminal output; low-current (50µA max) buffered average of selected ECG leads.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS1194CPAGR
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads1194cpagr-etched.step / ads1194cpagr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1194cpagr.step / ads1194cpagr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (81 pp, sha256 3923a51be1b79af3, retrieved 2026-09-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF