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ADS114S08IRHBT

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionads114s08irhbtfactory-2.0.0extractor-text

Verified ADS114S08IRHBT

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS114S08IRHBT · VQFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 113-page datasheet
  • ✓distributor: lcsc C2863225, digikey 296-47167-2-ND, mouser 595-ADS114S08IRHBT
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ut5_4p5d/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads114s08irhbt.kicad_sym✓ ads114s08irhbt.kicad_mod✓ ads114s08irhbt.step
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ADS114S08IRHBT

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)

ADS114S08IRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AINCOM passive Common analog input for single-ended measurements.
2 AIN5 passive Analog input 5.
3 AIN4 passive Analog input 4.
4 AIN3 passive Analog input 3.
5 AIN2 passive Analog input 2.
6 AIN1 passive Analog input 1.
7 AIN0 passive Analog input 0.
8 START/SYNC input Digital input that starts conversion; the rising edge starts a new conversion when synchronized.
9 CS input Active-low chip select that enables the serial interface; DOUT/DRDY is high-impedance when CS is high.
10 DIN input Serial data input latched on the SCLK falling edge.
11 SCLK input Serial clock input; Schmidt-triggered and noise-filtered, with data latched on the falling edge.
12 DOUT/DRDY output Serial data output combined with data-ready indication; active low.
13 DRDY output Active-low data-ready output that goes low when conversion data are ready.
14 DGND power_in Digital ground.
15 IOVDD power_in Digital I/O power supply; if not tied to DVDD, connect a 100-nF (or larger) capacitor to DGND.
16 DVDD power_in Digital core power supply; connect a 100-nF (or larger) capacitor to DGND.
17 CLK input External clock input; connect to DGND to use the internal oscillator.
18 RESET input Active-low reset input.
19 GPIO3/AIN11 bidirectional General-purpose I/O 3 (logic levels based on analog supply) and analog input 11 on the ADS114S08 only.
20 GPIO2/AIN10 bidirectional General-purpose I/O 2 (logic levels based on analog supply) and analog input 10 on the ADS114S08 only.
21 GPIO1/AIN9 bidirectional General-purpose I/O 1 (logic levels based on analog supply) and analog input 9 on the ADS114S08 only.
22 GPIO0/AIN8 bidirectional General-purpose I/O 0 (logic levels based on analog supply) and analog input 8 on the ADS114S08 only.
23 REFOUT output Positive voltage reference output; connect a 1-µF to 47-µF capacitor to REFCOM when the internal reference is enabled.
24 REFCOM output Negative voltage reference output; connect to AVSS.
25 NC unconnected Leave unconnected or connect to AVSS.
26 AVDD power_in Positive analog power supply; connect a 330-nF (or larger) capacitor to AVSS.
27 AVSS power_in Negative analog power supply.
28 AVSS-SW power_in Negative analog power supply for the low-side switch; connect to AVSS.
29 REFN0 passive Negative external reference input 0.
30 REFP0 passive Positive external reference input 0.
31 REFN1/AIN7 passive Negative external reference input 1; analog input 7 on the ADS114S08 only.
32 REFP1/AIN6 passive Positive external reference input 1; analog input 6 on the ADS114S08 only.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category ADC/DAC/Data Conversion
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power-supply voltage AVDD to AVSS -0.3 5.5 V 5
AVSS to DGND -2.8 0.3 V 5
DVDD to DGND -0.3 3.9 V 5
IOVDD to DGND -0.3 5.5 V 5
Continuous input current AVSS-SW, REFN0, REFOUT -100 100 mA Continuous 5
Continuous input current, all other pins except power-supply pins -10 10 mA Continuous 5
Junction temperature TJ 150 °C Junction 5
Storage temperature Tstg -60 150 °C Storage 5
Analog power supply AVDD to AVSS 2.7 5.25 V 6
AVSS to DGND -2.625 0 0.05 V 6
AVDD to DGND 1.5 5.25 V 6
Digital core power supply DVDD to DGND 2.7 3.6 V 6
Digital IO power supply IOVDD to DGND 5.25 V 6
Differential reference input voltage VREF 0.5 V VREF = V(REFPx) - V(REFNx) 6
External clock frequency fCLK 2 4.096 4.5 MHz 6
External clock duty cycle 40 50 60 % 6
Operating ambient temperature TA -50 125 °C 6
Input offset voltage VIO -120 20 120 µV TA = 25°C, PGA bypassed 7
Input offset voltage VIO -15 2 15 µV TA = 25°C, PGA enabled, gain = 16 to 128 7
Offset drift -75 10 75 nV/°C TA = -40°C to +85°C, PGA bypassed 7
Offset drift -100 15 100 nV/°C TA = -40°C to +85°C, PGA enabled, gain = 1 to 128 7
Integral nonlinearity (best fit) INL 1 10 ppmFSR PGA bypassed, VCM = AVDD / 2 7
Integral nonlinearity (best fit) INL 2 15 ppmFSR PGA enabled, gain = 1 to 8, VCM = AVDD / 2 7
Integral nonlinearity (best fit) INL 3 15 ppmFSR PGA enabled, gain = 16 to 128, VCM = AVDD / 2, TA = -40°C to +85°C 7
Internal reference accuracy VREF -0.1 0.01 0.1 % TA = 25°C, VQFN package 9
Internal reference temperature drift VREF 2.5 8 ppm/°C TA = -40°C to +85°C 9
Internal reference temperature drift VREF 3 10 ppm/°C TA = -50°C to +125°C 9
Internal reference output current -5 5 mA AVDD = 2.7 V to 3.3 V, sink and source 9
Internal reference output current -10 10 mA AVDD = 3.3 V to 5.25 V, sink and source 9
Capacitive load stability on REFOUT 1 47 µF Capacitor on REFOUT 9
Internal oscillator accuracy fCLK -1.5 1.5 % 9
IDAC accuracy (each IDAC) -5 0.7 5 % TA = 25°C, 10 µA to 100 µA 9
IDAC accuracy (each IDAC) -3 0.5 3 % TA = 25°C, 250 µA to 2 mA 9
Current mismatch between IDACs 0.15 0.8 % TA = 25°C, 10 µA to 100 µA 9
Current mismatch between IDACs 0.1 0.6 % TA = 25°C, 250 µA to 750 µA 9
Temperature drift (each IDAC) 20 120 ppm/°C 10 µA to 750 µA 9
Temperature drift (each IDAC) 10 80 ppm/°C 1 mA to 2 mA 9
Temperature drift matching between IDACs 3 25 ppm/°C 10 µA to 100 µA 9
Supply voltage monitor accuracy -1 1 % (AVDD - AVSS) / 4 monitor 10
Low-side power switch on-resistance RON 1 3 Ω On-resistance 10
Reference detection threshold 2 accuracy -3 1 3 % 10
Analog supply current, power-down mode IAVDD 0.1 1.5 µA AVDD = 3.3 V, power-down mode 11
Analog supply current, conversion mode PGA enabled gain 1, 2 IAVDD 120 135 µA AVDD = 3.3 V, conversion mode, PGA enabled, gain = 1, 2 11
Analog supply current, conversion mode PGA enabled gain 4, 8 IAVDD 140 155 µA AVDD = 3.3 V, conversion mode, PGA enabled, gain = 4, 8 11
Analog supply current, conversion mode PGA enabled gain 16, 32 IAVDD 165 180 µA AVDD = 3.3 V, conversion mode, PGA enabled, gain = 16, 32 11
Digital supply current, conversion mode IDVDD + IIOVDD 225 300 µA DVDD = IOVDD = 3.3 V, conversion mode, internal oscillator 11
SCLK period tc(SC) 100 ns 12
Pulse duration, SCLK high tw(SCH) 40 ns 12
Pulse duration, SCLK low tw(SCL) 40 ns 12
Setup time, DIN valid before SCLK falling edge tsu(DI) 15 ns 12
Hold time, DIN valid after SCLK falling edge th(DI) 20 ns 12
Junction-to-ambient thermal resistance RθJA 45.2 °C/W VQFN (RHB) 32 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 28.3 °C/W VQFN (RHB) 32 pins 6
Junction-to-board thermal resistance RθJB 15.8 °C/W VQFN (RHB) 32 pins 6
Junction-to-top characterization parameter ψJT 0.4 °C/W VQFN (RHB) 32 pins 6
Junction-to-board characterization parameter ψJB 15.7 °C/W VQFN (RHB) 32 pins 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.3 °C/W VQFN (RHB) 32 pins 6

CAD (KiCad official)

  • Symbol: ADS114S08IRHBT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ads114s08irhbt-etched.step / ads114s08irhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads114s08irhbt.step / ads114s08irhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (113 pp, sha256 225f7c18eaf8c8e5, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF