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ADS114S06IRHBR

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS114S06IRHBR

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)

ADS114S06IRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AINCOM input Common analog input for single-ended measurements.
2 AIN5 input Analog input 5.
3 AIN4 input Analog input 4.
4 AIN3 input Analog input 3.
5 AIN2 input Analog input 2.
6 AIN1 input Analog input 1.
7 AIN0 input Analog input 0.
8 START/SYNC input Digital input that starts conversion.
9 CS input Chip select; active low.
10 DIN input Serial data input.
11 SCLK input Serial clock input.
12 DOUT/DRDY output Serial data output combined with data ready; active low.
13 DRDY output Data ready; active low.
14 DGND power_in Digital ground.
15 IOVDD power_in Digital I/O power supply; if IOVDD is not tied to DVDD, connect a 100-nF (or larger) capacitor to DGND.
16 DVDD power_in Digital core power supply; connect a 100-nF (or larger) capacitor to DGND.
17 CLK input External clock input; connect to DGND to use the internal oscillator.
18 RESET input Reset; active low.
19 GPIO3/AIN11 bidirectional General-purpose I/O with logic levels based on the analog supply; analog input 11 on ADS114S08 only.
20 GPIO2/AIN10 bidirectional General-purpose I/O with logic levels based on the analog supply; analog input 10 on ADS114S08 only.
21 GPIO1/AIN9 bidirectional General-purpose I/O with logic levels based on the analog supply; analog input 9 on ADS114S08 only.
22 GPIO0/AIN8 bidirectional General-purpose I/O with logic levels based on the analog supply; analog input 8 on ADS114S08 only.
23 REFOUT output Positive voltage reference output; connect a 1-µF to 47-µF capacitor to REFCOM if the internal voltage reference is enabled.
24 REFCOM passive Negative voltage reference output; connect to AVSS.
25 NC unconnected Leave unconnected or connect to AVSS.
26 AVDD power_in Positive analog power supply; connect a 330-nF (or larger) capacitor to AVSS.
27 AVSS power_in Negative analog power supply.
28 AVSS-SW power_in Negative analog power supply for the low-side switch; connect to AVSS.
29 REFN0 input Negative external reference input 0.
30 REFP0 input Positive external reference input 0.
31 REFN1/AIN7 input Negative external reference input 1; analog input 7 on ADS114S08 only.
32 REFP1/AIN6 input Positive external reference input 1; analog input 6 on ADS114S08 only.
33 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category ADC/DAC/Data Conversion
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog power supply AVDD to AVSS 2.7 5.25 V 6
AVSS to DGND -2.625 0 0.05 V 6
AVDD to DGND 1.5 5.25 V 6
Digital core power supply DVDD to DGND 2.7 3.6 V 6
IOVDD to DGND 5.25 V 6
External clock frequency fCLK 2 4.096 4.5 MHz 6
External clock duty cycle 40 50 60 % 6
Operating ambient temperature TA -50 125 °C 6
Power-supply voltage AVDD to AVSS -0.3 5.5 V 5
Power-supply voltage AVSS to DGND -2.8 0.3 V 5
Power-supply voltage DVDD to DGND -0.3 3.9 V 5
Power-supply voltage IOVDD to DGND -0.3 5.5 V 5
Continuous input current AVSS-SW, REFN0, REFOUT -100 100 mA Continuous 5
Continuous input current all other pins except power-supply pins -10 10 mA Continuous 5
Junction temperature TJ 150 °C 5
Storage temperature Tstg -60 150 °C 5
Input offset voltage VIO -120 20 120 µV TA = 25°C, PGA bypassed 7
Input offset voltage VIO -15 2 15 µV TA = 25°C, PGA enabled, gain = 16 to 128 7
Offset drift -75 10 75 nV/°C TA = -40°C to +85°C, PGA bypassed 7
Offset drift -100 15 100 nV/°C TA = -40°C to +85°C, PGA enabled, gain = 1 to 128 7
Gain error 40 120 ppm TA = 25°C, PGA bypassed 8
Internal reference output voltage VREF 2.5 V 9
Internal reference accuracy -0.1 0.01 0.1 % TA = 25°C, VQFN package 9
Internal reference temperature drift 2.5 8 ppm/°C TA = -40°C to +85°C 9
Internal reference temperature drift 3 10 ppm/°C TA = -50°C to +125°C 9
Internal oscillator accuracy fCLK -1.5 1.5 % 9
IDAC accuracy (each IDAC) -5 0.7 5 % TA = 25°C, 10 µA to 100 µA 9
IDAC accuracy (each IDAC) -3 0.5 3 % TA = 25°C, 250 µA to 2 mA 9
Current mismatch between IDACs 0.15 0.8 % TA = 25°C, 10 µA to 100 µA 9
Current mismatch between IDACs 0.1 0.6 % TA = 25°C, 250 µA to 750 µA 9
Current mismatch between IDACs 0.07 0.4 % TA = 25°C, 1 mA to 2 mA 9
Temperature drift (each IDAC) 20 120 ppm/°C 10 µA to 750 µA 9
Temperature drift matching between IDACs 3 25 ppm/°C 10 µA to 100 µA 9
Temperature drift matching between IDACs 2 15 ppm/°C 250 µA to 2 mA 9
Analog supply current, power-down mode IAVDD 0.1 1.5 µA AVDD = 3.3 V, power-down mode 11
Analog supply current, conversion mode PGA enabled gain = 1, 2 IAVDD 120 135 µA AVDD = 3.3 V, external reference, PGA enabled 11
Analog supply current, conversion mode PGA enabled gain = 4, 8 IAVDD 140 155 µA AVDD = 3.3 V, external reference, PGA enabled 11
Analog supply current, conversion mode PGA enabled gain = 16, 32 IAVDD 165 180 µA AVDD = 3.3 V, external reference, PGA enabled 11
Digital input current -1 1 µA DGND ≤ VDigital Input ≤ IOVDD 10
Digital supply current, conversion mode internal oscillator IDVDD + IIOVDD 225 300 µA DVDD = IOVDD = 3.3 V, internal oscillator 11
Power dissipation PD 1.75 mW Conversion mode, PGA enabled, gain = 1 11
SCLK period tc(SC) 100 ns 12
Pulse duration, SCLK high tw(SCH) 40 ns 12
Setup time, DIN valid before SCLK falling edge tsu(DI) 15 ns 12
Hold time, DIN valid after SCLK falling edge th(DI) 20 ns 12
Delay time, first SCLK rising edge after CS falling edge td(CSSC) 20 ns 12
Delay time, CS rising edge after final SCLK falling edge td(SCCS) 20 ns 12
Pulse duration, RESET low tw(RSL) 4 tCLK 12
Propagation delay time, CS falling edge to DOUT driven tp(CSDO) 0 25 ns 12
Propagation delay time, SCLK rising edge to valid new DOUT tp(SCDO) 3 30 ns 12
Propagation delay time, CS rising edge to DOUT high impedance tp(CSDOZ) 0 25 ns 12
Junction-to-ambient thermal resistance, VQFN (RHB) RθJA 45.2 °C/W VQFN (RHB) 32 pins 6
Junction-to-case (top) thermal resistance, VQFN (RHB) RθJC(top) 28.3 °C/W VQFN (RHB) 32 pins 6
Junction-to-board thermal resistance, VQFN (RHB) RθJB 15.8 °C/W VQFN (RHB) 32 pins 6
Junction-to-top characterization parameter, VQFN (RHB) ψJT 0.4 °C/W VQFN (RHB) 32 pins 6
Junction-to-board characterization parameter, VQFN (RHB) ψJB 15.7 °C/W VQFN (RHB) 32 pins 6
Junction-to-case (bottom) thermal resistance, VQFN (RHB) RθJC(bot) 2.3 °C/W VQFN (RHB) 32 pins 6

CAD (KiCad official)

  • Symbol: ADS114S06IRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ads114s06irhbr-etched.step / ads114s06irhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads114s06irhbr.step / ads114s06irhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (111 pp, sha256 5d58be7761cdda6b, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF