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ADS1147IPWR

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Texas Instruments Analog To Digital Converters (ADC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs ads1147ipwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers ads1147ipwr: symbol viewer · Ray 6d ago
ads1147ipwr-etched.fit.json ads1147ipwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1147ipwr-etched.glb ads1147ipwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1147ipwr-etched.step ads1147ipwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1147ipwr.glb Publish 0.1.0 · Ray 1mo ago
ads1147ipwr.kicad_mod Publish 0.1.0 · Ray 1mo ago
ads1147ipwr.kicad_sym ads1147ipwr: symbol repaired (body fitted to the names) · Ray 6d ago
ads1147ipwr.lbr ads1147ipwr: symbol repaired (body fitted to the names) · Ray 6d ago
ads1147ipwr.step Publish 0.1.0 · Ray 1mo ago
package.json ads1147ipwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json ads1147ipwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md Initial commit: component/ads1147ipwr · Ray 1mo ago

ADS1147IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-20

ADS1147IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVDD power_in Digital power supply input 2.7 to 5.25 V with 0.1 µF bypass capacitor connected to DGND for decoupling.
2 DGND power_in Digital ground reference.
3 CLK input External clock input accepting 1 to 4.5 MHz frequency with 25% to 75% duty cycle, or tie to DGND to enable internal oscillator.
4 RESET input Active-low reset input with minimum pulse width 4 tCLK that restores all registers to default values.
5 REFP0/GPIO0 bidirectional Positive external reference input 0 accepting 0.5 to AVDD-AVSS-1 V, or general-purpose digital input/output pin 0.
6 REFN0/GPIO1 bidirectional Negative external reference input 0, or general-purpose digital input/output pin 1.
7 VREFOUT output Positive internal reference voltage output at 2.048 V nominal with ±10 mA output current capability and 1 to 47 µF load capacitor to VREFCOM.
8 VREFCOM output Negative internal reference voltage output connected to AVSS for unipolar or mid-voltage ground when using bipolar supply.
9 AIN0/IEXC input Analog input 0 from AVSS-100 mV to AVDD+100 mV with optional excitation current output capability when IDAC is routed to this channel.
10 AIN1/IEXC input Analog input 1 from AVSS-100 mV to AVDD+100 mV with optional excitation current output capability.
11 AIN2/IEXC/GPIO2 bidirectional Analog input 2 from AVSS-100 mV to AVDD+100 mV with optional excitation current output, or general-purpose digital input/output pin 2.
12 AIN3/IEXC/GPIO3 bidirectional Analog input 3 from AVSS-100 mV to AVDD+100 mV with optional excitation current output, or general-purpose digital input/output pin 3.
13 AVSS power_in Negative analog power supply from -2.65 to 0.1 V relative to DGND for proper analog circuit biasing and operation.
14 AVDD power_in Positive analog power supply 2.7 to 5.25 V with 0.1 µF bypass capacitor connected to AVSS for power supply noise reduction.
15 START input Active-high conversion start input with minimum pulse width 3 tCLK to initiate ADC conversion or hold high for continuous conversion.
16 CS input Active-low chip select for SPI communication with minimum high pulse duration 5 tCLK that resets serial interface when taken high.
17 DRDY output Data ready output active-low indicating new ADC conversion result is available in the output register.
18 DOUT/DRDY output Serial data output that functions as DOUT only when DRDY MODE bit is 0, or as combined DOUT/DRDY when DRDY MODE bit is 1.
19 DIN input Serial data input for SPI commands shifted on SCLK falling edge with setup time 5 ns before and hold time 5 ns after falling edge.
20 SCLK input Serial clock input for SPI interface with minimum period 488 ns and duty cycle 25% to 75% for reliable communication.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: ADS1147IPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ads1147ipwr-etched.step / ads1147ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1147ipwr.step / ads1147ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (100 pp, sha256 45e0fc75c85fcf9e, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF