main
Ray ads1120: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) 140f0bc 26d ago
{
  "schema_version": 1,
  "type": "component",
  "slug": "ads1120",
  "title": "ADS1120",
  "brief": "TI 16-bit, low-power delta-sigma ADC, TSSOP-16. PGA, mux, internal reference, IDACs for RTD sensing. Datasheet-verified.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "data-converter",
    "adc",
    "delta-sigma",
    "16-bit",
    "rtd",
    "tssop-16",
    "texas-instruments"
  ],
  "component": {
    "mpn": "ADS1120",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Converter",
    "subcategory": "Delta-sigma ADC",
    "datasheet": "https://www.ti.com/lit/ds/symlink/ads1120.pdf",
    "parts": {
      "symbol": "ads1120.kicad_sym",
      "footprint": "ads1120.kicad_mod",
      "model_3d": "ads1120-etched.glb",
      "model_3d_plain": "ads1120.glb",
      "model_3d_step": "ads1120-etched.step",
      "model_3d_step_plain": "ads1120.step",
      "lbr": "ads1120.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "SCLK",
        "type": "input",
        "description": "SPI serial clock input (mode 1: CPOL=0, CPHA=1). Idle low; data shifted on rising/falling edges as defined by the timing spec."
      },
      {
        "number": "2",
        "name": "CS",
        "type": "input",
        "description": "SPI chip-select input, active-low. Enables the serial interface; connect to DGND if the interface is always active (single-device systems)."
      },
      {
        "number": "3",
        "name": "CLK",
        "type": "input",
        "description": "External clock source input. Accepts 0.5 MHz to 4.5 MHz (nominal 4.096 MHz). Connect to DGND to select the internal oscillator."
      },
      {
        "number": "4",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground reference for DVDD and all digital I/O."
      },
      {
        "number": "5",
        "name": "AVSS",
        "type": "power_in",
        "description": "Negative analog power supply. Unipolar operation: tie to DGND (0 V). Bipolar operation: nominally -2.5 V (AVDD-AVSS range 2.3 V to 5.5 V)."
      },
      {
        "number": "6",
        "name": "AIN3/REFN1",
        "type": "input",
        "description": "Analog input channel 3, also negative reference input 1. An internal low-side power switch is connected between this pin and AVSS to allow bridge/RTD excitation control."
      },
      {
        "number": "7",
        "name": "AIN2",
        "type": "input",
        "description": "Analog input channel 2. Routed through the input MUX to the low-noise PGA and 16-bit delta-sigma modulator."
      },
      {
        "number": "8",
        "name": "REFN0",
        "type": "input",
        "description": "Negative reference input 0. Absolute voltage range AVSS-0.1 V to (VREFPx - 0.75 V); differential VREF 0.75 V to (AVDD-AVSS)."
      },
      {
        "number": "9",
        "name": "REFP0",
        "type": "input",
        "description": "Positive reference input 0. Absolute voltage range (VREFNx + 0.75 V) to (AVDD + 0.1 V)."
      },
      {
        "number": "10",
        "name": "AIN1",
        "type": "input",
        "description": "Analog input channel 1. Routed through the input MUX to the low-noise PGA and 16-bit delta-sigma modulator."
      },
      {
        "number": "11",
        "name": "AIN0/REFP1",
        "type": "input",
        "description": "Analog input channel 0, also positive reference input 1. Function selected via configuration registers."
      },
      {
        "number": "12",
        "name": "AVDD",
        "type": "power_in",
        "description": "Positive analog power supply. 2.3 V to 5.5 V (AVDD - AVSS). Decouple with a 100 nF (or larger) capacitor to AVSS."
      },
      {
        "number": "13",
        "name": "DVDD",
        "type": "power_in",
        "description": "Positive digital power supply. 2.3 V to 5.5 V (DVDD - DGND). Decouple with a 100 nF (or larger) capacitor to DGND."
      },
      {
        "number": "14",
        "name": "DRDY",
        "type": "output",
        "description": "Data-ready output, active-low. Falls when a new conversion result is available in the output register. Leave unconnected or tie to DVDD via a weak pull-up if unused."
      },
      {
        "number": "15",
        "name": "DOUT/DRDY",
        "type": "output",
        "description": "SPI serial data output (MISO), combined with data-ready indication (active-low). Driven on SCLK falling edges when CS is low."
      },
      {
        "number": "16",
        "name": "DIN",
        "type": "input",
        "description": "SPI serial data input (MOSI). Sampled on SCLK rising edges when CS is low."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/ads1120.pdf",
        "pages": 81,
        "sha256": "8ab70775ba04096c",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ads1120.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ads1120-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "c768bcaca7f251a16d70bf1d7cd3597563b90b160146979f9ff0cea144583271",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Type": "16-bit delta-sigma ADC",
      "Channels": "4 single-ended / 2 differential (mux)",
      "PGA": "Gain 1 to 128",
      "Reference": "Internal 2.048 V or external",
      "Excitation": "Two matched IDACs (RTD/thermistor)",
      "Data rate": "Up to 2 kSPS",
      "Supply": "2.3-5.5 V",
      "Package": "TSSOP-16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ads1120",
    "16-bit adc",
    "rtd adc",
    "delta sigma adc pga"
  ],
  "discovery_pitch": "TI ADS1120 16-bit delta-sigma ADC (TSSOP-16) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ads1120.kicad_sym",
    "ads1120.kicad_mod",
    "ads1120.glb",
    "ads1120.step",
    "ads1120.lbr",
    "docs/hero.png",
    "docs/ads1120-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ads1120-etched.step"
  ]
}