component
ADRF6520ACPZ
Public Made by Adomby adom
Analog Devices RF Amplifiers, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ADRF6520ACPZ
Analog Devices · RF Amplifiers · LFCSP-32(5x5)
ADRF6520ACPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INP1 | input | Channel 1 differential input with 100 Ω differential input impedance. |
| 2 | INM1 | input | Channel 1 differential input with 100 Ω differential input impedance. |
| 3 | COM | power_in | Analog common; connect to external circuit common using the lowest possible impedance. |
| 4 | CFLT1 | passive | Averaging capacitor for RMS detector; may be left open for the fastest response time and least rms averaging. |
| 5 | CFLT2 | passive | Averaging capacitor for RMS detector; may be left open for the fastest response time and least rms averaging. |
| 6 | COM | power_in | Analog common; connect to external circuit common using the lowest possible impedance. |
| 7 | INM2 | input | Channel 2 differential input with 100 Ω differential input impedance. |
| 8 | INP2 | input | Channel 2 differential input with 100 Ω differential input impedance. |
| 9 | RST | input | Active-low SPI reset to default bit values; TTL levels VLOW < 0.8 V and VHIGH > 2 V. |
| 10 | SCLK | input | SPI port clock; TTL levels VLOW < 0.8 V and VHIGH > 2 V. |
| 11 | SDIO | bidirectional | SPI data input and output; TTL levels VLOW < 0.8 V and VHIGH > 2 V. |
| 12 | VPS | power_in | Analog positive supply voltage, 3.15 V to 3.45 V. |
| 13 | VPS | power_in | Analog positive supply voltage, 3.15 V to 3.45 V. |
| 14 | COM | power_in | Analog common; connect to external circuit common using the lowest possible impedance. |
| 15 | CHP2 | passive | DC offset correction loop capacitor; connect to circuit common. |
| 16 | VRMS | output | RMS detector output with 1 V/V rms scaling; load with at least 1 kΩ to ground or the output will not reach full scale. |
| 17 | OPP2 | output | Channel 2 differential output with 20 Ω differential output impedance. |
| 18 | OPM2 | output | Channel 2 differential output with 20 Ω differential output impedance. |
| 19 | COM | power_in | Analog common; connect to external circuit common using the lowest possible impedance. |
| 20 | VGN2 | input | VGA2 analog gain control, operating from 0 V to 1.5 V with 30 mV/dB gain scaling. |
| 21 | VGN1 | input | VGA1 analog gain control, operating from 0 V to 1.5 V with 30 mV/dB gain scaling. |
| 22 | COM | power_in | Analog common; connect to external circuit common using the lowest possible impedance. |
| 23 | OPM1 | output | Channel 1 differential output with 20 Ω differential output impedance. |
| 24 | OPP1 | output | Channel 1 differential output with 20 Ω differential output impedance. |
| 25 | ENBL | input | Chip enable; pull high to enable, voltages below 1.6 V disable the device. |
| 26 | CHP1 | passive | DC offset correction loop capacitor; connect to circuit common. |
| 27 | COM | power_in | Analog common; connect to external circuit common using the lowest possible impedance. |
| 28 | VPS | power_in | Analog positive supply voltage, 3.15 V to 3.45 V. |
| 29 | VPS | power_in | Analog positive supply voltage, 3.15 V to 3.45 V. |
| 30 | COMD | power_in | Digital common; connect to external circuit common using the lowest possible impedance. |
| 31 | VPSD | power_in | Digital positive supply voltage, 3.15 V to 3.45 V. |
| 32 | CS | input | Active-low SPI chip select; TTL levels VLOW < 0.8 V and VHIGH > 2 V. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category | Radio Frequency Chip/Antenna |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Corner Frequency Absolute Accuracy | fC | -8 | 8 | % | Over operating temperature range | 3 | |
| Corner Frequency Matching | fC | -0.5 | 0.5 | % | Channel A and Channel B at same gain and bandwidth settings | 3 | |
| Gain Matching | -0.1 | 0.1 | dB | Channel A and Channel B at same gain and bandwidth settings; 1 kHz to fC | 3 | ||
| Group Delay Matching Corner Frequency = 36 MHz | -60 | 60 | ps | At fC/2; Channel A and Channel B at same gain | 3 | ||
| Group Delay Matching Corner Frequency = 144 MHz | -50 | 50 | ps | At fC/2; Channel A and Channel B at same gain | 3 | ||
| Group Delay Matching Corner Frequency = 720 MHz | -15 | 15 | ps | At fC/2; Channel A and Channel B at same gain | 3 | ||
| Group Delay Matching Bypass Mode | -10 | 10 | ps | At fC/2; Channel A and Channel B at same gain | 3 | ||
| Attenuation Range | -30 | 0 | dB | Each attenuator; VGN1 or VGN2 = 1.5 V | 3 | ||
| Output Load | 1 | kΩ | To reach full scale (RMS detector VRMS load) | 3 | |||
| Output Current | 3 | mA | Source available (VRMS output) | 3 | |||
| Input High Voltage | VHIGH | 2 | V | 5 | |||
| Input Low Voltage | VLOW | 0.8 | V | 5 | |||
| Input Current | IHIGH/ILOW | 1 | µA | 5 | |||
| Supply Voltage Range | VPS, VPSD | 3.15 | 3.3 | 3.45 | V | 5 | |
| Total Supply Current Maximum bandwidth setting | 425 | mA | ENBL = 3.3 V; maximum bandwidth setting | 5 | |||
| Disable Current | 10 | mA | ENBL = 0 V | 5 | |||
| Operating Temperature Range | -40 | 85 | °C | 6 | |||
| Supply Voltages | VPS, VPSD | 3.6 | V | 6 | |||
| Internal Power Dissipation | 1.53 | W | 6 | ||||
| Maximum Junction Temperature | 125 | °C | 6 | ||||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Lead Temperature | 300 | °C | Soldering 60 sec | 6 | |||
| Thermal Resistance θJA | θJA | 29.4 | °C/W | CP-32-12 package; JEDEC JESD51 simulation, 2S2P board | 6 | ||
| Thermal Resistance θJC | θJC | 2 | °C/W | CP-32-12 package; JEDEC JESD51 simulation, 1S0P board | 6 |
CAD (KiCad official)
- Symbol:
ADRF6520ACPZ - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
adrf6520acpz-etched.step/adrf6520acpz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adrf6520acpz.step/adrf6520acpz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (29 pp, sha256
cc04ee695ebaed0a, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).