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ADR4550CRZ

Analog Devices · Voltage References · SOIC-8

ADR4550CRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NIC unconnected Not Internally Connected; this pin is not connected internally.
2 VIN power_in Input voltage connection, specified for a supply range of 3 V to 15 V (16 V absolute maximum).
3 NIC unconnected Not Internally Connected; this pin is not connected internally.
4 GND power_in Ground.
5 NIC unconnected Not Internally Connected; this pin is not connected internally.
6 VOUT power_out Output voltage, able to source 10 mA and sink up to 10 mA per the features list.
7 NIC unconnected Not Internally Connected; this pin is not connected internally.
8 DNC unconnected Do Not Connect; do not connect to this pin.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Power Supply Chip
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Initial Output Voltage Error VOUT_ERR -0.02 0.02 % C Grade 8
Initial Output Voltage Error VOUT_ERR 1 mV B, C, D Grade 8
Solder Heat Resistance Shift -0.02 0.02 % A, B, C, D Grade 8
Temperature Coefficient (box method) TCVOUT 1 ppm/°C C Grade, 0°C ≤ TA ≤ +70°C (box method) 8
Temperature Coefficient (bowtie method) TCVOUT 2 ppm/°C C Grade, 0°C ≤ TA ≤ +70°C (bowtie method) 8
Line Regulation ΔVOUT/ΔVIN 1 10 ppm/V −40°C ≤ TA ≤ +125°C 8
Load Regulation (source) ΔVOUT/ΔIL 25 80 ppm/mA A, B, C Grade, IL = 0 mA to +10 mA source, −40°C ≤ TA ≤ +125°C 8
Load Regulation (sink) ΔVOUT/ΔIL 35 120 ppm/mA A, B, C Grade, IL = 0 mA to −10 mA sink, −40°C ≤ TA ≤ +125°C 8
Quiescent Current IQ 700 950 μA −40°C ≤ TA ≤ +125°C, no load 8
Dropout Voltage VDO 100 mV −40°C ≤ TA ≤ +125°C, no load 8
Dropout Voltage VDO 300 mV −40°C ≤ TA ≤ +125°C, IL = 2 mA 8
Output Current Capacity, Sinking IL -10 mA Sinking 8
Output Current Capacity, Sourcing IL 10 mA Sourcing 8
Load Capacitance 0.1 100 µF 9
Input Voltage Range VIN 5.1 15 V IL = 0 mA, TA = 25°C 8
Operating Temperature Range (C grade) 0 70 °C ADR4550 C and D Grade only 10
Output Voltage VOUT 5 V 8
Ripple Rejection Ratio RRR 90 dB fIN = 1 kHz 8
Output Voltage Noise eNp-p 2.8 μV p-p 0.1 Hz to 10.0 Hz 8
Output Voltage Noise Density eN 95.3 nV/√Hz 1 kHz 8
Output Voltage Hysteresis ΔVOUT_HYS -13 ppm A, B, C Grade, +25°C to +125°C to −40°C to +25°C (full cycle) 8
Output Voltage Hysteresis ΔVOUT_HYS -97 ppm 25°C to 125°C to 25°C (half cycle) 9
Output Voltage Hysteresis ΔVOUT_HYS -8 ppm 25°C to 70°C to 0°C to 25°C (full cycle) 9
Output Voltage Hysteresis ΔVOUT_HYS -17 ppm 25°C to 70°C to 25°C (half cycle) 9
Long-Term Drift, 250 hours ΔVOUT_LTD 19 ppm A, B, C Grade, TA = 25°C, 250 hours (early life drift) 9
Long-Term Drift, 1000 hours ΔVOUT_LTD 25 ppm A, B, C Grade, TA = 25°C, 1000 hours 9
Long-Term Drift, 4500 hours ΔVOUT_LTD 51 ppm A, B, C Grade, TA = 25°C, 4500 hours 9
Turn-On Settling Time tR 160 µs COUT = 0.1 µF, CIN = 0.1 µF, RLOAD = 1 kΩ 9
Supply Voltage 16 V TA = 25°C 10
Operating Temperature Range (C and D grade) 0 70 °C ADR4525, ADR4540, ADR4550 C and D Grade Only 10
Storage Temperature Range -65 150 °C 10
Junction Temperature Range -65 150 °C 10
ESD Human Body Model HBM 6 kV 10
Thermal Resistance Junction to Ambient, 8-Lead SOIC θJA 120 °C/W 2-Layer JEDEC Board 10
Thermal Resistance Junction to Case, 8-Lead SOIC θJC 63 °C/W 1-Layer JEDEC Board 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs is packaged in a SOIC plastic package and has a moisture sensi￾tivity level of MSL-1, per the JEDEC standard. However, moisture absorption from the air into the package changes the internal 38

CAD (KiCad official)

  • Symbol: ADR4550CRZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: adr4550crz-etched.step / adr4550crz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adr4550crz.step / adr4550crz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (41 pp, sha256 de2dca59e24477c2, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF