ADR4540BRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NIC	unconnected	Not internally connected; this pin is not connected internally.
2	VIN	power_in	Input voltage connection; the datasheet specifies an input voltage range of 3 V to 15 V and a supply absolute maximum of 16 V.
3	NIC	unconnected	Not internally connected; this pin is not connected internally.
4	GND	power_in	Ground connection for the reference.
5	NIC	unconnected	Not internally connected; this pin is not connected internally.
6	VOUT	power_out	Output voltage of the reference; the datasheet rates the output current at +10 mA source and −10 mA sink.
7	NIC	unconnected	Not internally connected; this pin is not connected internally.
8	DNC	unconnected	Do not connect; nothing should be connected to this pin.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-8
Category	Power Management ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Initial output voltage error, B grade	VOUT_ERR	-0.02		0.02	%		7
Initial output voltage error, B grade (absolute)	VOUT_ERR			820	μV		7
Solder heat resistance shift		-0.02		0.02	%		7
Temperature coefficient, box method, B grade	TCVOUT			2	ppm/°C	−40°C ≤ TA ≤ +125°C (box method)	7
Temperature coefficient, bowtie method, B grade	TCVOUT			4	ppm/°C	−40°C ≤ TA ≤ +125°C (bowtie method)	7
Line regulation	ΔVOUT/ΔVIN		1	10	ppm/V	−40°C ≤ TA ≤ +125°C	7
Load regulation, sourcing	ΔVOUT/ΔIL		25	80	ppm/mA	IL = 0 mA to +10 mA source, −40°C ≤ TA ≤ +125°C	7
Load regulation, sinking	ΔVOUT/ΔIL		50	120	ppm/mA	IL = 0 mA to −10 mA sink, −40°C ≤ TA ≤ +125°C	7
Quiescent current	IQ		700	950	μA	−40°C ≤ TA ≤ +125°C, no load	7
Dropout voltage, no load	VDO		100		mV	−40°C ≤ TA ≤ +125°C, no load	7
Dropout voltage, IL = 2 mA	VDO		300		mV	−40°C ≤ TA ≤ +125°C, IL = 2 mA	7
Output current capacity, sinking	IL	-10			mA		7
Output current capacity, sourcing	IL			10	mA		7
Ripple rejection ratio	RRR		90		dB	fIN = 1 kHz	7
Output voltage noise, 0.1 Hz to 10 Hz	eNp-p		2.7		μV p-p	0.1 Hz to 10.0 Hz	7
Output voltage noise density	eN		83.5		nV/√Hz	1 kHz	7
Output voltage	VOUT		4.096		V		7
Output voltage hysteresis, full cycle −40°C	ΔVOUT_HYS		-13		ppm	TA cycled +25°C to +125°C to −40°C to +25°C (full cycle)	7
Output voltage hysteresis, half cycle 125°C	ΔVOUT_HYS		-97		ppm	25°C to 125°C to 25°C (half cycle)	7
Output voltage hysteresis, full cycle 70°C	ΔVOUT_HYS		-8		ppm	25°C to 70°C to 0°C to 25°C (full cycle)	7
Output voltage hysteresis, half cycle 70°C	ΔVOUT_HYS		-17		ppm	25°C to 70°C to 25°C (half cycle)	7
Long-term drift, 250 hours	ΔVOUT_LTD		19		ppm	TA = 25°C, 250 hours (early life drift)	7
Long-term drift, 1000 hours	ΔVOUT_LTD		25		ppm	TA = 25°C, 1000 hours	7
Long-term drift, 4500 hours	ΔVOUT_LTD		51		ppm	TA = 25°C, 4500 hours	8
Turn-on settling time	tR		155		µs	COUT = 0.1 µF, CIN = 0.1 µF, RLOAD = 1 kΩ	8
Load capacitance		0.1		100	µF		8
Input voltage range	VIN	4.2		15	V		7
Supply voltage				16	V		10
Operating temperature range		-40		125	°C		10
Storage temperature range		-65		150	°C		10
Junction temperature range		-65		150	°C		10
Electrostatic discharge, human body model				6	kV	Human Body Model (HBM)	10
Thermal resistance, junction to air, 2-layer JEDEC board	θJA			120	°C/W	8-Lead SOIC, 2-Layer JEDEC Board	10
Thermal resistance, junction to case, 1-layer JEDEC board	θJC		63		°C/W	8-Lead SOIC, 1-Layer JEDEC Board	10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		is packaged in a SOIC plastic package and has a moisture sensitivity level of MSL-1, per the JEDEC standard. However, moisture absorption from the air into the package changes the internal	38

CAD (KiCad official)

Symbol: ADR4540BRZ
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: adr4540brz-etched.step / adr4540brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adr4540brz.step / adr4540brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (41 pp, sha256 de2dca59e24477c2, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADR4540BRZ

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3D Model

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