# ADR4525BRZ

**Analog Devices** · Voltage Reference · SOIC-8

ADR4525BRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NIC | unconnected | Internally not connected; the datasheet states this pin is not connected internally. |
| 2 | VIN | power_in | Input voltage connection, with a specified operating input range of 3 V to 15 V and an absolute maximum rating of 16 V. |
| 3 | NIC | unconnected | Internally not connected; the datasheet states this pin is not connected internally. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | NIC | unconnected | Internally not connected; the datasheet states this pin is not connected internally. |
| 6 | VOUT | power_out | Reference voltage output (2.500 V for the ADR4525), rated for +10 mA source and −10 mA sink current. |
| 7 | NIC | unconnected | Internally not connected; the datasheet states this pin is not connected internally. |
| 8 | DNC | unconnected | Do not connect; the datasheet instructs that this pin must not be connected. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage | VOUT |  | 2.5 |  | V |  | 5 |
| Initial output voltage error, B grade | VOUT_ERR | -0.02 |  | 0.02 | % | B grade, initial error | 5 |
| Initial output voltage error, B grade (absolute) | VOUT_ERR |  |  | 500 | µV | B grade | 5 |
| Temperature coefficient, B grade, box method | TCVOUT |  |  | 2 | ppm/°C | −40°C ≤ TA ≤ +125°C (box method) | 5 |
| Temperature coefficient, B grade, bow-tie method | TCVOUT |  |  | 4 | ppm/°C | −40°C ≤ TA ≤ +125°C (bow-tie method) | 5 |
| Line regulation | ΔVOUT/ΔVIN |  | 1 | 10 | ppm/V | −40°C ≤ TA ≤ +125°C | 5 |
| Load regulation, source | ΔVOUT/ΔIL |  | 30 | 80 | ppm/mA | IL = 0 mA to +10 mA source, −40°C ≤ TA ≤ +125°C | 5 |
| Load regulation, sink | ΔVOUT/ΔIL |  | 60 | 120 | ppm/mA | IL = 0 mA to −10 mA sink, −40°C ≤ TA ≤ +125°C | 5 |
| Quiescent current | IQ |  | 700 | 950 | µA | −40°C ≤ TA ≤ +125°C, no load | 5 |
| Dropout voltage, no load | VDO |  |  | 500 | mV | −40°C ≤ TA ≤ +125°C, no load | 5 |
| Dropout voltage, IL = 2 mA | VDO |  |  | 500 | mV | −40°C ≤ TA ≤ +125°C, IL = 2 mA | 5 |
| Ripple rejection ratio | RRR |  | 90 |  | dB | fIN = 1 kHz | 5 |
| Output current capability, sink | IL | -10 |  |  | mA |  | 5 |
| Output current capability, source | IL |  |  | 10 | mA |  | 5 |
| Output voltage noise | eNp-p |  | 1.25 |  | µV p-p | 0.1 Hz to 10.0 Hz | 5 |
| Output voltage noise density | eN |  | 41.3 |  | nV/√Hz | 1 kHz | 5 |
| Thermal hysteresis, full cycle | ΔVOUT_HYS |  | -13 |  | ppm | +25°C to +125°C to −40°C to +25°C | 5 |
| Thermal hysteresis, half cycle | ΔVOUT_HYS |  | -97 |  | ppm | 25°C to 125°C to 25°C | 5 |
| Long-term drift, early | ΔVOUT_LTD |  | 19 |  | ppm | TA = 25°C, 250 hours | 5 |
| Long-term drift, 1000 h | ΔVOUT_LTD |  | 25 |  | ppm | TA = 25°C, 1000 hours | 5 |
| Long-term drift, 4500 h | ΔVOUT_LTD |  | 51 |  | ppm | TA = 25°C, 4500 hours | 5 |
| Turn-on settling time | tRR |  | 125 |  | µs | COUT = 1 µF, CIN = 0.1 µF, RLOAD = 1 kΩ | 5 |
| Load capacitance |  |  | 1 | 100 | µF |  | 5 |
| Input voltage | VIN | 3 |  | 15 | V | Specifications at VIN = 3 V to 15 V | 5 |
| Operating temperature range, B grade | TA | -40 |  | 125 | °C | B grade | 10 |
| Supply voltage | VIN |  |  | 16 | V |  | 10 |
| Operating temperature range | TA | -40 |  | 125 | °C |  | 10 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 10 |
| Junction temperature range | TJ | -65 |  | 150 | °C |  | 10 |
| ESD human body model |  |  |  | 6 | kV | Human body model (HBM) | 10 |
| Thermal resistance, junction-to-case | θJC |  | 63 |  | °C/W | Table row for 1-layer JEDEC board; 100 µm TIM | 10 |
| Thermal resistance, junction-to-ambient | θJA |  | 120 |  | °C/W | 2-layer JEDEC board | 10 |

## CAD (KiCad official)

- Symbol: `ADR4525BRZ`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adr4525brz-etched.step` / `adr4525brz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adr4525brz.step` / `adr4525brz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883814127321088) (37 pp, sha256 `48d4d0fe0ae23886`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adr4525brz-datasheet.pdf)