component
ADR4520ARZ-R7
Public Made by Adomby adom
Analog Devices Voltage Reference, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADR4520ARZ-R7
Analog Devices · Voltage Reference · SOIC-8
ADR4520ARZ-R7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 2 | VIN | power_in | Input voltage connection supplying the reference, with an input voltage range of 3 V to 15 V stated in the features section. |
| 3 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 4 | GND | power_in | Ground connection. |
| 5 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 6 | VOUT | power_out | Output voltage of the reference, rated +10 mA source / −10 mA sink according to the features section. |
| 7 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 8 | DNC | unconnected | Do Not Connect; do not connect anything to this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Initial output voltage error (A grade) | VOUT_ERR | -0.04 | 0.04 | % | A grade | 4 | |
| Initial output voltage error (A grade, voltage form) | VOUT_ERR | 820 | μV | A grade | 4 | ||
| Solder heat resistance shift | -0.02 | 0.02 | % | 4 | |||
| Temperature coefficient, box method (A grade) | TCVOUT | 4 | ppm/°C | −40°C ≤ TA ≤ +125°C (box method) | 4 | ||
| Temperature coefficient, bowtie method (A grade) | TCVOUT | 8 | ppm/°C | −40°C ≤ TA ≤ +125°C (bowtie method) | 4 | ||
| Line regulation | ΔVOUT/ΔVIN | 1 | 10 | ppm/V | −40°C ≤ TA ≤ +125°C | 4 | |
| Load regulation (sourcing) | ΔVOUT/ΔIL | 30 | 80 | ppm/mA | IL = 0 mA to +10 mA source, −40°C ≤ TA ≤ +125°C | 4 | |
| Load regulation (sinking) | ΔVOUT/ΔIL | 100 | 120 | ppm/mA | IL = 0 mA to −10 mA sink, −40°C ≤ TA ≤ +125°C | 4 | |
| Quiescent current | IQ | 700 | 950 | μA | −40°C ≤ TA ≤ +125°C, no load | 4 | |
| Dropout voltage (no load) | VDO | 1 | V | −40°C ≤ TA ≤ +125°C, no load | 4 | ||
| Dropout voltage (IL = 2 mA) | VDO | 1 | V | −40°C ≤ TA ≤ +125°C, IL = 2 mA | 4 | ||
| Output current capacity, sinking | IL | -8 | mA | Sinking | 4 | ||
| Output current capacity, sourcing | IL | 10 | mA | Sourcing | 4 | ||
| Load capacitance | 1 | 100 | µF | 4 | |||
| Input voltage range | VIN | 3 | 15 | V | Supply voltage (VIN), IL = 0 mA, TA = 25°C | 4 | |
| Supply voltage (absolute maximum) | VIN | 16 | V | 10 | |||
| Operating temperature range | -40 | 125 | °C | A grade | 10 | ||
| Storage temperature range | -65 | 150 | °C | 10 | |||
| Junction temperature range | -65 | 150 | °C | 10 | |||
| ESD, Human Body Model | 6 | kV | HBM | 10 | |||
| Thermal resistance, junction to air | θJA | 120 | °C/W | 8-lead SOIC, 2-layer JEDEC board | 10 | ||
| Thermal resistance, junction to case | θJC | 63 | °C/W | 8-lead SOIC, 1-layer JEDEC board | 10 | ||
| Ripple rejection ratio | RRR | 90 | dB | fIN = 1 kHz | 4 | ||
| Output voltage noise, 0.1 Hz to 10 Hz | eNp-p | 1 | μV p-p | 0.1 Hz to 10.0 Hz | 4 | ||
| Output voltage noise density | eN | 35.8 | nV/√Hz | 1 kHz | 4 | ||
| Output voltage hysteresis, full cycle 25°C→125°C→−40°C→25°C | ΔVOUT_HYS | -13 | ppm | Temperature cycled from +25°C to +125°C to −40°C to +25°C (full cycle) | 4 | ||
| Output voltage hysteresis, half cycle 25°C→125°C→25°C | ΔVOUT_HYS | -97 | ppm | 25°C to 125°C to 25°C (half cycle) | 4 | ||
| Output voltage hysteresis, full cycle 25°C→70°C→0°C→25°C | ΔVOUT_HYS | -8 | ppm | 25°C to 70°C to 0°C to 25°C (full cycle) | 4 | ||
| Output voltage hysteresis, half cycle 25°C→70°C→25°C | ΔVOUT_HYS | -17 | ppm | 25°C to 70°C to 25°C (half cycle) | 4 | ||
| Long-term drift, early life | ΔVOUT_LTD | 19 | ppm | TA = 25°C, 250 hours (early life drift) | 4 | ||
| Long-term drift, 1000 hours | ΔVOUT_LTD | 25 | ppm | TA = 25°C, 1000 hours | 4 | ||
| Long-term drift, 4500 hours | ΔVOUT_LTD | 51 | ppm | TA = 25°C, 4500 hours | 4 | ||
| Turn-on settling time | tR | 90 | µs | COUT = 1 µF, CIN = 0.1 µF, RLOAD = 1 kΩ | 4 |
CAD (KiCad official)
- Symbol:
ADR4520ARZ-R7 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adr4520arz-r7-etched.step/adr4520arz-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adr4520arz-r7.step/adr4520arz-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (40 pp, sha256
047cc7b047b9ba6e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADR4520ARZ-R7
**Analog Devices** · Voltage Reference · SOIC-8
ADR4520ARZ-R7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 2 | VIN | power_in | Input voltage connection supplying the reference, with an input voltage range of 3 V to 15 V stated in the features section. |
| 3 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 4 | GND | power_in | Ground connection. |
| 5 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 6 | VOUT | power_out | Output voltage of the reference, rated +10 mA source / −10 mA sink according to the features section. |
| 7 | NIC | unconnected | Not Internally Connected; this pin is not connected internally. |
| 8 | DNC | unconnected | Do Not Connect; do not connect anything to this pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Initial output voltage error (A grade) | VOUT_ERR | -0.04 | | 0.04 | % | A grade | 4 |
| Initial output voltage error (A grade, voltage form) | VOUT_ERR | | | 820 | μV | A grade | 4 |
| Solder heat resistance shift | | -0.02 | | 0.02 | % | | 4 |
| Temperature coefficient, box method (A grade) | TCVOUT | | | 4 | ppm/°C | −40°C ≤ TA ≤ +125°C (box method) | 4 |
| Temperature coefficient, bowtie method (A grade) | TCVOUT | | | 8 | ppm/°C | −40°C ≤ TA ≤ +125°C (bowtie method) | 4 |
| Line regulation | ΔVOUT/ΔVIN | | 1 | 10 | ppm/V | −40°C ≤ TA ≤ +125°C | 4 |
| Load regulation (sourcing) | ΔVOUT/ΔIL | | 30 | 80 | ppm/mA | IL = 0 mA to +10 mA source, −40°C ≤ TA ≤ +125°C | 4 |
| Load regulation (sinking) | ΔVOUT/ΔIL | | 100 | 120 | ppm/mA | IL = 0 mA to −10 mA sink, −40°C ≤ TA ≤ +125°C | 4 |
| Quiescent current | IQ | | 700 | 950 | μA | −40°C ≤ TA ≤ +125°C, no load | 4 |
| Dropout voltage (no load) | VDO | | | 1 | V | −40°C ≤ TA ≤ +125°C, no load | 4 |
| Dropout voltage (IL = 2 mA) | VDO | | | 1 | V | −40°C ≤ TA ≤ +125°C, IL = 2 mA | 4 |
| Output current capacity, sinking | IL | -8 | | | mA | Sinking | 4 |
| Output current capacity, sourcing | IL | | | 10 | mA | Sourcing | 4 |
| Load capacitance | | 1 | | 100 | µF | | 4 |
| Input voltage range | VIN | 3 | | 15 | V | Supply voltage (VIN), IL = 0 mA, TA = 25°C | 4 |
| Supply voltage (absolute maximum) | VIN | | | 16 | V | | 10 |
| Operating temperature range | | -40 | | 125 | °C | A grade | 10 |
| Storage temperature range | | -65 | | 150 | °C | | 10 |
| Junction temperature range | | -65 | | 150 | °C | | 10 |
| ESD, Human Body Model | | | | 6 | kV | HBM | 10 |
| Thermal resistance, junction to air | θJA | | 120 | | °C/W | 8-lead SOIC, 2-layer JEDEC board | 10 |
| Thermal resistance, junction to case | θJC | | 63 | | °C/W | 8-lead SOIC, 1-layer JEDEC board | 10 |
| Ripple rejection ratio | RRR | | 90 | | dB | fIN = 1 kHz | 4 |
| Output voltage noise, 0.1 Hz to 10 Hz | eNp-p | | 1 | | μV p-p | 0.1 Hz to 10.0 Hz | 4 |
| Output voltage noise density | eN | | 35.8 | | nV/√Hz | 1 kHz | 4 |
| Output voltage hysteresis, full cycle 25°C→125°C→−40°C→25°C | ΔVOUT_HYS | | -13 | | ppm | Temperature cycled from +25°C to +125°C to −40°C to +25°C (full cycle) | 4 |
| Output voltage hysteresis, half cycle 25°C→125°C→25°C | ΔVOUT_HYS | | -97 | | ppm | 25°C to 125°C to 25°C (half cycle) | 4 |
| Output voltage hysteresis, full cycle 25°C→70°C→0°C→25°C | ΔVOUT_HYS | | -8 | | ppm | 25°C to 70°C to 0°C to 25°C (full cycle) | 4 |
| Output voltage hysteresis, half cycle 25°C→70°C→25°C | ΔVOUT_HYS | | -17 | | ppm | 25°C to 70°C to 25°C (half cycle) | 4 |
| Long-term drift, early life | ΔVOUT_LTD | | 19 | | ppm | TA = 25°C, 250 hours (early life drift) | 4 |
| Long-term drift, 1000 hours | ΔVOUT_LTD | | 25 | | ppm | TA = 25°C, 1000 hours | 4 |
| Long-term drift, 4500 hours | ΔVOUT_LTD | | 51 | | ppm | TA = 25°C, 4500 hours | 4 |
| Turn-on settling time | tR | | 90 | | µs | COUT = 1 µF, CIN = 0.1 µF, RLOAD = 1 kΩ | 4 |
## CAD (KiCad official)
- Symbol: `ADR4520ARZ-R7`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adr4520arz-r7-etched.step` / `adr4520arz-r7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adr4520arz-r7.step` / `adr4520arz-r7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589803691633893376) (40 pp, sha256 `047cc7b047b9ba6e`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adr4520arz-r7-datasheet.pdf)