component
ADP7142AUJZ-R7
Public Made by Adomby adom
Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TSOT-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADP7142AUJZ-R7
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-5
ADP7142AUJZ-R7 from Analog Devices, in a TSOT-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Regulator input supply, operating range 2.7 V to 40 V (absolute maximum −0.3 V to +44 V); bypass VIN to GND with a 2.2 µF or larger capacitor. |
| 2 | GND | power_in | Ground reference for the regulator. |
| 3 | EN | input | Enable input: high starts the regulator, low shuts it down (absolute maximum −0.3 V to +44 V); connect EN to VIN for automatic start-up. |
| 4 | SENSE/ADJ | input | Sense input connected to the load that also serves as the adjust node, where an external resistor divider can set the output above the fixed voltage (absolute maximum −0.3 V to +6 V). |
| 5 | VOUT | power_out | Regulated output voltage; bypass VOUT to GND with a 2.2 µF or larger capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | 40 | V | 3 | ||
| Output voltage accuracy | VOUT | -0.8 | 0.8 | % | IOUT = 10 mA, TJ = 25°C | 3 | |
| Output voltage accuracy | VOUT | -1.2 | 1.5 | % | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V, TJ = -40°C to +85°C | 3 | |
| Output voltage accuracy | VOUT | -1.8 | 1.8 | % | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V | 3 | |
| Line regulation | ΔVOUT/ΔVIN | -0.01 | 0.01 | %/V | VIN = (VOUT + 1 V) to 40 V | 3 | |
| Load regulation | ΔVOUT/ΔIOUT | 0.002 | 0.004 | %/mA | ΔIOUT = 100 μA to 200 mA | 3 | |
| Dropout voltage | VDROPOUT | 30 | 60 | mV | IOUT = 10 mA | 3 | |
| Dropout voltage | VDROPOUT | 200 | 420 | mV | IOUT = 200 mA | 3 | |
| Output noise | OUTNOISE | 11 | µV rms | 10 Hz to 100 kHz, all output voltage options | 3 | ||
| Power supply rejection ratio | PSRR | 88 | dB | 10 kHz, VIN = 7 V, VOUT = 5 V | 3 | ||
| Power supply rejection ratio | PSRR | 68 | dB | 100 kHz, VIN = 7 V, VOUT = 5 V | 3 | ||
| Power supply rejection ratio | PSRR | 50 | dB | 1 MHz, VIN = 7 V, VOUT = 5 V | 3 | ||
| SENSE input bias current | I-BIAS | 10 | 1000 | nA | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V | 3 | |
| Startup time | tSTART-UP | 380 | µs | VOUT = 5 V | 3 | ||
| Ground current | IGND | 50 | 80 | µA | IOUT = 0 µA | 3 | |
| Thermal shutdown threshold | TSSD | 150 | °C | 3 | |||
| Thermal shutdown hysteresis | TSSD-HYS | 15 | °C | 3 | |||
| Input and output capacitance, minimum | CMIN | 1.5 | µF | TA = -40°C to +125°C | 4 | ||
| Capacitor equivalent series resistance (ESR) | RESR | 0.001 | 0.3 | Ω | TA = -40°C to +125°C | 4 | |
| VIN to GND | -0.3 | 44 | V | 5 | |||
| VOUT to GND | -0.3 | V | max = VIN (as printed: −0.3 V to VIN) | 5 | |||
| EN to GND | -0.3 | 44 | V | 5 | |||
| SENSE/ADJ to GND | -0.3 | 6 | V | 5 | |||
| SS to GND | -0.3 | V | max = lesser of VIN or +6 V (as printed) | 5 | |||
| Storage temperature range | -65 | 150 | °C | 5 | |||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Operating ambient temperature range | TA | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance (5-lead TSOT) | θJA | 170 | °C/W | 4-layer board, worst case, surface-mount | 5 | ||
| Junction-to-board thermal characterization parameter (5-lead TSOT) | ΨJB | 43 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
ADP7142AUJZ-R7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-5 (KiCad packages3D, STEP)
- 3D model files:
adp7142aujz-r7-etched.step/adp7142aujz-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp7142aujz-r7.step/adp7142aujz-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (23 pp, sha256
d59e22ad1ee0f9a4, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADP7142AUJZ-R7
**Analog Devices** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-5
ADP7142AUJZ-R7 from Analog Devices, in a TSOT-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Regulator input supply, operating range 2.7 V to 40 V (absolute maximum −0.3 V to +44 V); bypass VIN to GND with a 2.2 µF or larger capacitor. |
| 2 | GND | power_in | Ground reference for the regulator. |
| 3 | EN | input | Enable input: high starts the regulator, low shuts it down (absolute maximum −0.3 V to +44 V); connect EN to VIN for automatic start-up. |
| 4 | SENSE/ADJ | input | Sense input connected to the load that also serves as the adjust node, where an external resistor divider can set the output above the fixed voltage (absolute maximum −0.3 V to +6 V). |
| 5 | VOUT | power_out | Regulated output voltage; bypass VOUT to GND with a 2.2 µF or larger capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | | 40 | V | | 3 |
| Output voltage accuracy | VOUT | -0.8 | | 0.8 | % | IOUT = 10 mA, TJ = 25°C | 3 |
| Output voltage accuracy | VOUT | -1.2 | | 1.5 | % | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V, TJ = -40°C to +85°C | 3 |
| Output voltage accuracy | VOUT | -1.8 | | 1.8 | % | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V | 3 |
| Line regulation | ΔVOUT/ΔVIN | -0.01 | | 0.01 | %/V | VIN = (VOUT + 1 V) to 40 V | 3 |
| Load regulation | ΔVOUT/ΔIOUT | | 0.002 | 0.004 | %/mA | ΔIOUT = 100 μA to 200 mA | 3 |
| Dropout voltage | VDROPOUT | | 30 | 60 | mV | IOUT = 10 mA | 3 |
| Dropout voltage | VDROPOUT | | 200 | 420 | mV | IOUT = 200 mA | 3 |
| Output noise | OUTNOISE | | 11 | | µV rms | 10 Hz to 100 kHz, all output voltage options | 3 |
| Power supply rejection ratio | PSRR | | 88 | | dB | 10 kHz, VIN = 7 V, VOUT = 5 V | 3 |
| Power supply rejection ratio | PSRR | | 68 | | dB | 100 kHz, VIN = 7 V, VOUT = 5 V | 3 |
| Power supply rejection ratio | PSRR | | 50 | | dB | 1 MHz, VIN = 7 V, VOUT = 5 V | 3 |
| SENSE input bias current | I-BIAS | | 10 | 1000 | nA | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V | 3 |
| Startup time | tSTART-UP | | 380 | | µs | VOUT = 5 V | 3 |
| Ground current | IGND | | 50 | 80 | µA | IOUT = 0 µA | 3 |
| Thermal shutdown threshold | TSSD | | 150 | | °C | | 3 |
| Thermal shutdown hysteresis | TSSD-HYS | | 15 | | °C | | 3 |
| Input and output capacitance, minimum | CMIN | 1.5 | | | µF | TA = -40°C to +125°C | 4 |
| Capacitor equivalent series resistance (ESR) | RESR | 0.001 | | 0.3 | Ω | TA = -40°C to +125°C | 4 |
| VIN to GND | | -0.3 | | 44 | V | | 5 |
| VOUT to GND | | -0.3 | | | V | max = VIN (as printed: −0.3 V to VIN) | 5 |
| EN to GND | | -0.3 | | 44 | V | | 5 |
| SENSE/ADJ to GND | | -0.3 | | 6 | V | | 5 |
| SS to GND | | -0.3 | | | V | max = lesser of VIN or +6 V (as printed) | 5 |
| Storage temperature range | | -65 | | 150 | °C | | 5 |
| Junction temperature | TJ | | | 150 | °C | | 5 |
| Operating ambient temperature range | TA | -40 | | 125 | °C | | 5 |
| Junction-to-ambient thermal resistance (5-lead TSOT) | θJA | | 170 | | °C/W | 4-layer board, worst case, surface-mount | 5 |
| Junction-to-board thermal characterization parameter (5-lead TSOT) | ΨJB | | 43 | | °C/W | | 5 |
## CAD (KiCad official)
- Symbol: `ADP7142AUJZ-R7`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-5`
- 3D model: TSOT-5 (KiCad packages3D, STEP)
- 3D model files: `adp7142aujz-r7-etched.step` / `adp7142aujz-r7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adp7142aujz-r7.step` / `adp7142aujz-r7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893322554822656) (23 pp, sha256 `d59e22ad1ee0f9a4`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adp7142aujz-r7-datasheet.pdf)