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ADP5052ACPZ-R7

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Analog Devices DC-DC Converters, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADP5052ACPZ-R7

Analog Devices · DC-DC Converters · LFCSP-48(7x7)

ADP5052ACPZ-R7 from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST3 power_out Bootstrap supply for the channel 3 high-side FET driver, connected through a 0.1 µF X5R or X7R ceramic capacitor to SW3.
2 PGND3 power_in Power ground for channel 3.
3 SW3 output Channel 3 switch-node output.
4 PVIN3 power_in Channel 3 power input, bypassed to ground at this pin; the regulator input range is 4.5 V to 15 V.
5 EN5 input Channel 5 precision enable input with a 0.8 V threshold; an external resistor divider can set the start-up threshold.
6 FB5 input Channel 5 feedback sense input, with a 0.5 V reference for the adjustable output.
7 VOUT5 power_out Channel 5 output of the 200 mA LDO regulator.
8 PVIN5 power_in Channel 5 LDO power input, operating from 1.7 V to 5.5 V and bypassed to ground at this pin.
9 PVIN4 power_in Channel 4 power input, bypassed to ground at this pin; the regulator input range is 4.5 V to 15 V.
10 SW4 output Channel 4 switch-node output.
11 PGND4 power_in Power ground for channel 4.
12 BST4 power_out Bootstrap supply for the channel 4 high-side FET driver, connected through a 0.1 µF X5R or X7R ceramic capacitor to SW4.
13 GND power_in For internal test only; connect this pin to ground.
14 EN4 input Channel 4 precision enable input with a 0.8 V threshold; an external resistor divider can set the start-up threshold.
15 COMP4 passive Channel 4 error-amplifier output; an RC network is connected from this pin to ground.
16 FB4 input Channel 4 feedback sense input.
17 GND power_in For internal test only; connect this pin to ground.
18 GND power_in For internal test only; connect this pin to ground.
19 GND power_in For internal test only; connect this pin to ground.
20 PWRGD output Open-drain power-good output that reflects the status of the selected channel(s), with channel 1 monitored by default.
21 FB2 input Channel 2 feedback sense input; tie to ground to ignore channel 2 when channels 1 and 2 operate in parallel.
22 COMP2 passive Channel 2 error-amplifier output with an RC network to ground; it is left open in parallel operation.
23 EN2 input Channel 2 precision enable input with a 0.8 V threshold; tie to ground to ignore EN2 in parallel operation.
24 PVIN2 power_in Channel 2 power input, bypassed to ground at this pin; the regulator input range is 4.5 V to 15 V.
25 PVIN2 power_in Channel 2 power input, bypassed to ground at this pin; the regulator input range is 4.5 V to 15 V.
26 SW2 output Channel 2 switch-node output.
27 SW2 output Channel 2 switch-node output.
28 BST2 power_out Bootstrap supply for the channel 2 high-side FET driver, connected through a 0.1 µF X5R or X7R ceramic capacitor to SW2.
29 DL2 output Channel 2 low-side FET gate driver; a resistor from this pin to ground sets the channel 2 current limit.
30 PGND power_in Power ground for channels 1 and 2.
31 DL1 output Channel 1 low-side FET gate driver; a resistor from this pin to ground sets the channel 1 current limit.
32 BST1 power_out Bootstrap supply for the channel 1 high-side FET driver, connected through a 0.1 µF X5R or X7R ceramic capacitor to SW1.
33 SW1 output Channel 1 switch-node output.
34 SW1 output Channel 1 switch-node output.
35 PVIN1 power_in Input supply for the internal 5.1 V VREG regulator and the channel 1 buck regulator, bypassed to ground at this pin; PVIN1 must be above UVLO before other channels operate.
36 PVIN1 power_in Input supply for the internal 5.1 V VREG regulator and the channel 1 buck regulator, bypassed to ground at this pin; PVIN1 must be above UVLO before other channels operate.
37 EN1 input Channel 1 precision enable input with a 0.8 V threshold; an external resistor divider can set the start-up threshold.
38 SS12 passive Resistor divider between VREG and ground at this pin sets the soft-start time of channels 1 and 2 and selects parallel operation.
39 COMP1 passive Channel 1 error-amplifier output; an RC network is connected from this pin to ground.
40 FB1 input Channel 1 feedback sense input, with a 0.8 V reference for the adjustable output.
41 RT passive A resistor from RT to ground sets the switching frequency between 250 kHz and 1.4 MHz.
42 VDD power_out Output of the internal 3.3 V linear regulator, which requires a 1 µF ceramic capacitor to ground and is intended for internal circuits only.
43 SYNC/MODE bidirectional Sync input or output pin for frequency synchronization to a 250 kHz to 1.4 MHz clock, and MODE pin where logic high selects forced PWM and logic low selects auto PWM/PSM.
44 VREG power_out Output of the internal 5.1 V linear regulator, which requires a 1 µF ceramic capacitor to ground and supplies up to 95 mA total load including MOSFET driver current.
45 FB3 input Channel 3 feedback sense input.
46 COMP3 passive Channel 3 error-amplifier output; an RC network is connected from this pin to ground.
47 SS34 passive Resistor divider between VREG and ground at this pin sets the soft-start time of channels 3 and 4.
48 EN3 input Channel 3 precision enable input with a 0.8 V threshold; an external resistor divider can set the start-up threshold.
49 EPAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category Power Management (PMIC)
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage range VIN 4.5 15 V PVIN1、PVIN2、PVIN3、PVIN4引脚 4
Operating quiescent current, 4 bucks IQ(4-BUCKS) 4.8 6.25 mA 无切换，所有ENx引脚均为高电平 4
Shutdown current, 4 bucks + LDO ISHDN(4BUCKS+LDO) 25 65 µA 所有ENx引脚均为低电平 4
UVLO rising threshold VUVLO-RISING 4.2 4.36 V PVIN1、PVIN2、PVIN3、PVIN4引脚 4
UVLO falling threshold VUVLO-FALLING 3.6 3.78 V PVIN1、PVIN2、PVIN3、PVIN4引脚 4
Switching frequency fSW 700 740 780 kHz RT = 25.5 kΩ 4
Switching frequency range fSW 250 1400 kHz 4
SYNC input clock range fSYNC 250 1400 kHz 4
SYNC input high voltage VH(SYNC) 1.3 V 4
SYNC input low voltage VL(SYNC) 0.4 V 4
Precision enable high threshold VTH_H(EN) 0.806 0.832 V 4
Precision enable low threshold VTH_L(EN) 0.688 0.725 V 4
Internal power-good rising threshold VPWRGD(RISE) 86.3 90.5 95 % 4
PWRGD output low voltage VPWRGD_LOW 50 100 mV IPWRGD = 1 mA 4
VDD output voltage VVDD 3.2 3.305 3.4 V IVDD = 10 mA 4
VREG output voltage VVREG 4.9 5.1 5.3 V 4
VREG current limit ILIM_VREG 50 95 140 mA 4
Channel 1 FB1 feedback accuracy VFB1(DEFAULT) -0.55 0.55 % TJ = 25°C 5
Channel 1 FB1 feedback accuracy VFB1(DEFAULT) -1.25 1 % 0°C ≤ TJ ≤ 85°C 5
Channel 1 FB1 feedback accuracy VFB1(DEFAULT) -1.5 1.5 % −40°C ≤ TJ ≤ +125°C 5
Channel 1 high-side current limit, RILIM1 floating ITH(ILIM1) 3.5 4.4 5.28 A RILIM1 = 悬空 5
Channel 1 high-side current limit, RILIM1 = 47 kΩ ITH(ILIM1) 1.91 2.63 3.08 A RILIM1 = 47 kΩ 5
Channel 1 high-side current limit, RILIM1 = 22 kΩ ITH(ILIM1) 4.95 6.44 7.48 A RILIM1 = 22 kΩ 5
Channel 1 minimum on time tMIN_ON1 117 155 ns fSW = 250 kHz至1.4 MHz 5
Channel 1 programmable soft-start range 2 8 ms 5
Channel 2 FB2 feedback accuracy VFB2(DEFAULT) -0.55 0.55 % TJ = 25°C 5
Channel 2 FB2 feedback accuracy VFB2(DEFAULT) -1.25 1 % 0°C ≤ TJ ≤ 85°C 5
Channel 2 FB2 feedback accuracy VFB2(DEFAULT) -1.5 1.5 % −40°C ≤ TJ ≤ +125°C 5
Channel 2 high-side current limit, RILIM2 floating ITH(ILIM2) 3.5 4.4 5.28 A RILIM2 = 悬空 5
Channel 2 high-side current limit, RILIM2 = 47 kΩ ITH(ILIM2) 1.91 2.63 3.08 A RILIM2 = 47 kΩ 5
Channel 2 high-side current limit, RILIM2 = 22 kΩ ITH(ILIM2) 4.95 6.44 7.48 A RILIM2 = 22 kΩ 5
Channel 2 minimum on time tMIN_ON2 117 155 ns fSW = 250 kHz至1.4 MHz 5
Channel 3 FB3 feedback accuracy VFB3(DEFAULT) -0.55 0.55 % TJ = 25°C 6
Channel 3 FB3 feedback accuracy VFB3(DEFAULT) -1.25 1 % 0°C ≤ TJ ≤ 85°C 6
Channel 3 FB3 feedback accuracy VFB3(DEFAULT) -1.5 1.5 % −40°C ≤ TJ ≤ +125°C 6
Channel 3 peak current limit ITH(ILIM3) 1.7 2.2 2.55 A 6
Channel 3 minimum on time tMIN_ON3 90 120 ns fSW = 250 kHz至1.4 MHz 6
Channel 4 FB4 feedback accuracy VFB4(DEFAULT) -0.55 0.55 % TJ = 25°C 6
Channel 4 FB4 feedback accuracy VFB4(DEFAULT) -1.25 1 % 0°C ≤ TJ ≤ 85°C 6
Channel 4 FB4 feedback accuracy VFB4(DEFAULT) -1.5 1.5 % −40°C ≤ TJ ≤ +125°C 6
Channel 4 peak current limit ITH(ILIM4) 1.7 2.2 2.55 A 6
Channel 4 minimum on time tMIN_ON4 90 120 ns fSW = 250 kHz至1.4 MHz 6
LDO input supply voltage range 1.7 5.5 V PVIN5引脚 7
LDO bias current 30 130 µA IOUT5 = 200 µA 7
LDO bias current 60 170 µA IOUT5 = 10 mA 7
LDO bias current 145 320 µA IOUT5 = 200 mA 7
LDO FB5 feedback accuracy -1 1 % TJ = 25°C 7
LDO FB5 feedback accuracy -1.6 1.6 % 0°C ≤ TJ ≤ 85°C 7
LDO FB5 feedback accuracy -2 2 % −40°C ≤ TJ ≤ +125°C 7
LDO dropout voltage 80 mV IOUT5 = 200 mA, VOUT5 = 3.3 V 7
LDO dropout voltage 100 mV IOUT5 = 200 mA, VOUT5 = 2.5 V 7
LDO dropout voltage 180 mV IOUT5 = 200 mA, VOUT5 = 1.5 V 7
LDO current limit 250 510 mA 输出电压降至额定典型值的90% 7
PVIN1 to PGND absolute maximum -0.3 18 V 8
PVIN5 to GND absolute maximum -0.3 6.5 V 8
VREG to GND absolute maximum -0.3 6.5 V 8
EN1 to EN5 to GND absolute maximum -0.3 6.5 V 8
Operating junction temperature range TJ -40 125 °C 8
Junction-to-ambient thermal resistance, 48-lead LFCSP θJA 27.87 °C/W 48引脚 LFCSP 8
Junction-to-case thermal resistance, 48-lead LFCSP θJC 2.99 °C/W 48引脚 LFCSP 8

CAD (KiCad official)

  • Symbol: ADP5052ACPZ-R7
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: adp5052acpz-r7-etched.step / adp5052acpz-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adp5052acpz-r7.step / adp5052acpz-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (40 pp, sha256 321e6ba8cd61f859, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF