component
ADP2116ACPZ-R7
Public Made by Adomby adom
Analog Devices DC-DC Converters, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownADP2116ACPZ-R7
Analog Devices · DC-DC Converters · LFCSP-32(5x5)
ADP2116ACPZ-R7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground for the internal analog and digital circuits; connect to the signal/analog ground plane before connecting to the power ground. |
| 2 | COMP1 | output | Channel 1 error amplifier output; connect a series RC network from COMP1 to GND to compensate the loop, and tie COMP1 and COMP2 together for multiphase operation. |
| 3 | FREQ | input | Frequency select input; connect through a resistor to GND to set the switching frequency per Table 5. |
| 4 | SCFG | input | Synchronization configuration input; tie to VDD to make SYNC/CLKOUT an output or tie to GND to make it an input. |
| 5 | SYNC/CLKOUT | bidirectional | External synchronization input or internal clock output (set by SCFG); as an output it provides a buffered clock at twice the switching frequency with 90° phase shift, and as an input it synchronizes the converters to an external clock. |
| 6 | OPCFG | input | Operation configuration input; tie to VDD or connect through a resistor to GND to set the operating mode per Table 7, including peak current limit selection and pulse skip enable/disable. |
| 7 | COMP2 | output | Channel 2 error amplifier output; connect a series RC network from COMP2 to GND to compensate the loop, and tie COMP1 and COMP2 together for multiphase operation. |
| 8 | VDD | power_in | Power supply input for internal circuitry, specified from 2.75 V to 5.5 V; connect to VINx through a 10 Ω resistor as close as possible to the device and bypass to GND with 1 µF or greater. |
| 9 | FB2 | input | Channel 2 feedback input; connect to VOUT2 for fixed output, or to a resistor divider between VOUT2 and GND for adjustable output with a 0.6 V reference. |
| 10 | V2SET | input | Channel 2 output voltage set pin; connect through a resistor to GND for a fixed output (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V), or through 82 kΩ to GND or directly to VDD for adjustable output. |
| 11 | SS2 | passive | Channel 2 soft-start input; a capacitor from SS2 to GND sets the soft-start period, where 10 nF gives 1 ms, and SS2 is connected to SS1 in multiphase configurations. |
| 12 | PGOOD2 | output | Channel 2 open-drain power-good output; use a 100 kΩ pull-up to VDD or to a voltage of 5.5 V or less, and it is held low when Channel 2 is out of regulation. |
| 13 | EN2 | input | Channel 2 enable input; drive high to turn on and low to turn off the Channel 2 converter, tie to VDD for startup with VDD, and connect to EN1 in multiphase operation. |
| 14 | VIN4 | power_in | Power supply input and source of the high-side internal power MOSFET of Channel 2; VINx pins are rated up to 6 V with respect to PGND. |
| 15 | VIN5 | power_in | Power supply input and source of the high-side internal power MOSFET of Channel 2; VINx pins are rated up to 6 V with respect to PGND. |
| 16 | VIN6 | power_in | Power supply input and source of the high-side internal power MOSFET of Channel 2; VINx pins are rated up to 6 V with respect to PGND. |
| 17 | SW4 | output | Channel 2 switch node, the drain of the P-channel switch and N-channel synchronous rectifier; tie to SW3 and connect the output LC filter between this node and VOUT. |
| 18 | SW3 | output | Channel 2 switch node, the drain of the P-channel switch and N-channel synchronous rectifier; tie to SW4 and connect the output LC filter between this node and VOUT. |
| 19 | PGND4 | power_in | Channel 2 power ground, the source of the low-side internal power MOSFET; PGND1 through PGND4 are rated within 0.3 V of GND. |
| 20 | PGND3 | power_in | Channel 2 power ground, the source of the low-side internal power MOSFET; PGND1 through PGND4 are rated within 0.3 V of GND. |
| 21 | PGND2 | power_in | Channel 1 power ground, the source of the low-side internal power MOSFET; PGND1 through PGND4 are rated within 0.3 V of GND. |
| 22 | PGND1 | power_in | Channel 1 power ground, the source of the low-side internal power MOSFET; PGND1 through PGND4 are rated within 0.3 V of GND. |
| 23 | SW2 | output | Channel 1 switch node, the drain of the P-channel switch and N-channel synchronous rectifier; tie to SW1 and connect the output LC filter between this node and VOUT. |
| 24 | SW1 | output | Channel 1 switch node, the drain of the P-channel switch and N-channel synchronous rectifier; tie to SW2 and connect the output LC filter between this node and VOUT. |
| 25 | VIN3 | power_in | Power supply input and source of the high-side internal power MOSFET of Channel 1; VINx pins are rated up to 6 V with respect to PGND. |
| 26 | VIN2 | power_in | Power supply input and source of the high-side internal power MOSFET of Channel 1; VINx pins are rated up to 6 V with respect to PGND. |
| 27 | VIN1 | power_in | Power supply input and source of the high-side internal power MOSFET of Channel 1; VINx pins are rated up to 6 V with respect to PGND. |
| 28 | EN1 | input | Channel 1 enable input; drive high to turn on and low to turn off the Channel 1 converter, tie to VDD for startup with VDD, and connect to EN2 in multiphase operation. |
| 29 | PGOOD1 | output | Channel 1 open-drain power-good output; use a 100 kΩ pull-up to VDD or to a voltage of 5.5 V or less, and it is held low when Channel 1 is out of regulation. |
| 30 | SS1 | passive | Channel 1 soft-start input; a capacitor from SS1 to GND sets the soft-start period, where 10 nF gives 1 ms, and SS1 is connected to SS2 in multiphase configurations. |
| 31 | V1SET | input | Channel 1 output voltage set pin; connect through a resistor to GND for a fixed output (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V), or through 82 kΩ to GND or directly to VDD for adjustable output. |
| 32 | FB1 | input | Channel 1 feedback input; connect to VOUT1 for fixed output, or to a resistor divider between VOUT1 and GND for adjustable output with a 0.6 V reference. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Bias Voltage | VDD | 2.75 | 5.5 | V | 3 | ||
| Undervoltage Lockout Threshold (rising) | UVLO | 2.65 | 2.75 | V | VDD rising | 3 | |
| Undervoltage Lockout Threshold (falling) | UVLO | 2.35 | 2.47 | V | VDD falling | 3 | |
| Quiescent Current, Channel 1 | IDD,CH1 | 1.7 | 2.5 | mA | EN1 = VDD = 5 V, EN2 = GND, VFB1 = VDD, OPCFG = GND | 3 | |
| Quiescent Current, Channel 2 | IDD,CH2 | 1.7 | 2.5 | mA | EN2 = VDD = 5 V, EN1 = GND, VFB2 = VDD, OPCFG = GND | 3 | |
| Quiescent Current, Channel 1 + Channel 2 | IDD,CH1 + CH2 | 3 | 4 | mA | EN1 = EN2 = VDD = 5 V, VFB2 = VFB1 = VDD, OPCFG = GND | 3 | |
| Shutdown Current | IDD,SD | 1 | 10 | µA | EN1 = EN2 = GND, VDD = VINx = 2.75 V to 5.5 V, TJ = −40°C to +115°C | 3 | |
| FB1, FB2 Input Bias Current (adjustable output) | IFB | 1 | 65 | nA | Adjustable output, VFBx = 0.6 V, V1SET, V2SET = VDD or via 82 kΩ to GND | 4 | |
| COMPx Clamp High Voltage | VCOMP, HI | 2.36 | 2.45 | V | VDD = VINx = 2.75 V to 5.5 V | 3 | |
| COMPx Clamp Low Voltage | VCOMP, LO | 0.65 | 0.7 | V | VDD = VINx = 2.75 V to 5.5 V | 3 | |
| Output Voltage Accuracy, adjustable output (TJ = 25°C) | VFB | 0.597 | 0.6 | 0.603 | V | Adjustable output, TJ = 25°C, V1SET, V2SET = VDD or via 82 kΩ to GND | 3 |
| Output Voltage Accuracy, adjustable output (TJ = −40°C to +125°C) | VFB | 0.594 | 0.6 | 0.606 | V | Adjustable output, TJ = −40°C to +125°C, V1SET, V2SET = VDD or via 82 kΩ to GND | 3 |
| VFB Error, fixed output (TJ = 25°C) | VFB ERROR | -1 | 1 | % | Fixed output, TJ = 25°C, V1SET, V2SET = GND or via 4.7 kΩ, 8.2 kΩ, 15 kΩ, 27 kΩ, 47 kΩ to GND | 3 | |
| VFB Error, fixed output (TJ = −40°C to +125°C) | VFB ERROR | -1.5 | 1.5 | % | Fixed output, TJ = −40°C to +125°C, V1SET, V2SET = GND or via 4.7 kΩ, 8.2 kΩ, 15 kΩ, 27 kΩ, 47 kΩ to GND | 3 | |
| Switching Frequency | fSW | 255 | 300 | 345 | kHz | FREQ tied to GND | 3 |
| Switching Frequency | fSW | 510 | 600 | 690 | kHz | FREQ via 8.2 kΩ to GND | 3 |
| Switching Frequency | fSW | 1020 | 1200 | 1380 | kHz | FREQ via 27 kΩ to GND | 3 |
| SYNC Frequency Range | fSYNC | 400 | 1000 | kHz | fSYNC = 2 × fSW, FREQ tied to GND | 3 | |
| SYNC Frequency Range | fSYNC | 800 | 2000 | kHz | fSYNC = 2 × fSW, FREQ via 8.2 kΩ to GND | 3 | |
| SYNC Frequency Range | fSYNC | 1600 | 4000 | kHz | fSYNC = 2 × fSW, FREQ via 27 kΩ to GND | 3 | |
| CLKOUT Frequency | fCLKOUT | 510 | 600 | 690 | kHz | fCLKOUT = 2 × fSW, FREQ tied to GND | 4 |
| CLKOUT Frequency | fCLKOUT | 1020 | 1200 | 1380 | kHz | fCLKOUT = 2 × fSW, FREQ via 8.2 kΩ to GND | 4 |
| CLKOUT Frequency | fCLKOUT | 2040 | 2400 | 2760 | kHz | fCLKOUT = 2 × fSW, FREQ via 27 kΩ to GND | 4 |
| Peak Output Current Limit, Channel 1 | ILIMIT1 | 3.5 | 4.5 | 5.3 | A | OPCFG tied to VDD or via 82 kΩ to GND | 4 |
| Peak Output Current Limit, Channel 2 | ILIMIT2 | 3.5 | 4.5 | 5.3 | A | OPCFG tied to VDD or via 82 kΩ to GND | 4 |
| Peak Output Current Limit (reduced setting) | 2.4 | 3.3 | 4 | A | OPCFG via 47 kΩ or 27 kΩ to GND | 4 | |
| Hiccup Time | 10 | 13.6 | 17 | ms | fSW = 300 kHz | 4 | |
| SWx Maximum Leakage Current | 0.1 | 15 | µA | VDD = VINx = 2.75 V to 5.5 V, ENx = GND, TJ = −40°C to +115°C | 4 | ||
| EN1, EN2 Input Leakage Current | IEN_LEAK | 0.1 | 1 | µA | VDD = VINx = ENx = 2.75 V to 5.5 V, TJ = −40°C to +115°C | 4 | |
| SS1, SS2 Pin Current | ISS1, ISS2 | 4.8 | 6 | 7.8 | µA | VDD = VINx = 2.75 V to 5.5 V, VSS = 0 V | 4 |
| Overvoltage PGOODx Falling Threshold | 100 | 108 | 114 | % | Expressed as a percentage of the nominal output voltage | 4 | |
| Undervoltage PGOODx Rising Threshold | 85 | 92 | 97 | % | Expressed as a percentage of the nominal output voltage | 4 | |
| PGOODx Leakage Current | 0.1 | 1 | µA | VPGOODx = VDD | 4 | ||
| PGOODx Low Saturation Voltage | 50 | 110 | mV | IPGOODx = 1 mA | 4 | ||
| VDD to GND | VDD | -0.3 | 6 | V | 5 | ||
| VIN1 to VIN6 to PGND1 to PGND4 | VIN | -0.3 | 6 | V | 5 | ||
| EN1, EN2, SCFG, FREQ, SYNC/CLKOUT, PGOOD1, PGOOD2, V1SET, V2SET, COMP1, COMP2, SS1, SS2 to GND | -0.3 | V | Maximum printed as VDD + 0.3 V | 5 | |||
| FB1, FB2 to GND | FB | -0.3 | 3.6 | V | 5 | ||
| SW1, SW2, SW3, SW4 to PGND1, PGND2, PGND3, PGND4 | SW | -0.3 | V | Maximum printed as VDD + 0.3 V | 5 | ||
| PGND1, PGND2, PGND3, PGND4 to GND | 0.3 | V | Printed as 0.3 V; sign not shown in text | 5 | |||
| VIN1 to VIN6 to VDD | 0.3 | V | Printed as 0.3 V; sign not shown in text | 5 | |||
| Thermal Resistance, Junction-to-Ambient | θJA | 34 | °C/W | JEDEC 1S2P PCB, Natural Convection | 5 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 5 | ||
| Maximum Soldering Lead Temperature | 260 | °C | 10 sec | 5 |
CAD (KiCad official)
- Symbol:
ADP2116ACPZ-R7 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
adp2116acpz-r7-etched.step/adp2116acpz-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp2116acpz-r7.step/adp2116acpz-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (36 pp, sha256
25682e0b04bc5f78, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).