component
ADP1763ACPZ-R7
Public Made by Adomby adom
Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, LFCSP-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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Datasheet
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Contents
README
markdownADP1763ACPZ-R7
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · LFCSP-16-EP(3x3)
ADP1763ACPZ-R7 from Analog Devices, in a LFCSP-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Regulator input supply, specified from 1.10 V to 1.98 V; bypass to GND with a 10 µF or greater capacitor, and all four VIN pins must be connected to the source supply. |
| 2 | VIN | power_in | Regulator input supply, specified from 1.10 V to 1.98 V; bypass to GND with a 10 µF or greater capacitor, and all four VIN pins must be connected to the source supply. |
| 3 | VIN | power_in | Regulator input supply, specified from 1.10 V to 1.98 V; bypass to GND with a 10 µF or greater capacitor, and all four VIN pins must be connected to the source supply. |
| 4 | VIN | power_in | Regulator input supply, specified from 1.10 V to 1.98 V; bypass to GND with a 10 µF or greater capacitor, and all four VIN pins must be connected to the source supply. |
| 5 | REFCAP | passive | Reference filter capacitor: connect a 1 µF capacitor from REFCAP to ground and do not connect a load to ground. |
| 6 | VREG | power_in | Regulated input supply to the LDO amplifier: bypass to GND with a 1 µF or greater capacitor and do not connect a load to ground. |
| 7 | GND | power_in | Ground reference for the regulator; the exposed pad is electrically connected to this pin and should be tied to a PCB ground plane. |
| 8 | VADJ | passive | Adjustable voltage pin for the adjustable output option: a 10 kΩ resistor from VADJ to ground sets the output to 1.5 V, and the pin is left floating for fixed-output versions. |
| 9 | VOUT | power_out | Regulated output voltage: bypass to GND with a 10 µF or greater capacitor, and all four VOUT pins must be connected to the load. |
| 10 | VOUT | power_out | Regulated output voltage: bypass to GND with a 10 µF or greater capacitor, and all four VOUT pins must be connected to the load. |
| 11 | VOUT | power_out | Regulated output voltage: bypass to GND with a 10 µF or greater capacitor, and all four VOUT pins must be connected to the load. |
| 12 | VOUT | power_out | Regulated output voltage: bypass to GND with a 10 µF or greater capacitor, and all four VOUT pins must be connected to the load. |
| 13 | SENSE | input | Sense input that measures the actual output voltage at the load and feeds it to the error amplifier; connect it as close to the load as possible to minimize IR drop. |
| 14 | SS | passive | Soft-start pin: a 10 nF capacitor from SS to ground sets the start-up time to 0.6 ms. |
| 15 | PG | output | Open-drain power-good output that requires an external pull-up resistor and goes low in shutdown, current-limit or thermal shutdown mode, or when VOUT falls below 90% of nominal. |
| 16 | EN | input | Enable input: drive high to turn the regulator on and low to turn it off; connect EN to VIN for automatic startup. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage supply range | VIN | 1.1 | 1.98 | V | TJ = −40°C to +125°C | 3 | |
| Operating supply current | IGND | 4.5 | 8 | mA | ILOAD = 0 µA | 3 | |
| Operating supply current | IGND | 4.9 | 8 | mA | ILOAD = 10 mA | 3 | |
| Operating supply current | IGND | 5.5 | 8.5 | mA | ILOAD = 100 mA | 3 | |
| Operating supply current | IGND | 12 | 16 | mA | ILOAD = 3 A | 3 | |
| Shutdown current | IGND-SD | 180 | µA | TJ = −40°C to +85°C, VIN = (VOUT + 0.2 V) to 1.98 V | 3 | ||
| Shutdown current | IGND-SD | 800 | µA | TJ = 85°C to 125°C, VIN = (VOUT + 0.2 V) to 1.98 V | 3 | ||
| Output voltage range (fixed) | VOUT_FIXED | 0.9 | 1.5 | V | TA = 25°C | 3 | |
| Output voltage range (adjustable) | VOUT_ADJ | 0.5 | 1.5 | V | TA = 25°C | 3 | |
| Fixed output voltage accuracy | VOUT | -0.5 | 0.5 | % | ILOAD = 100 mA, TA = 25°C | 3 | |
| Fixed output voltage accuracy | VOUT | -1 | 1.5 | % | 10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to 1.98 V, TJ = 0°C to 85°C | 3 | |
| Fixed output voltage accuracy | VOUT | -1.5 | 1.5 | % | 10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to 1.98 V | 3 | |
| Adjustable pin current | IADJ | 49.5 | 50 | 50.5 | µA | TA = 25°C | 3 |
| Adjustable pin current | IADJ | 48.8 | 50 | 51 | µA | VIN = (VOUT + 0.2 V) to 1.98 V | 3 |
| Adjustable output voltage gain factor | AD | 2.95 | 3.055 | VIN = (VOUT + 0.2 V) to 1.98 V | 3 | ||
| Line regulation | ∆VOUT/∆VIN | -0.15 | 0.15 | %/V | VIN = (VOUT + 0.2 V) to 1.98 V | 3 | |
| Load regulation | ∆VOUT/∆IOUT | 0.12 | 0.45 | %/A | ILOAD = 10 mA to 3 A | 3 | |
| Dropout voltage | VDROPOUT | 12 | 23 | mV | ILOAD = 100 mA, VOUT ≥ 1.2 V | 3 | |
| Dropout voltage | VDROPOUT | 95 | 145 | mV | ILOAD = 3 A, VOUT ≥ 1.2 V | 3 | |
| Soft start current | ISS | 8 | 10 | 12 | µA | 1.1 V ≤ VIN ≤ 1.98 V | 3 |
| Current-limit threshold | ILIMIT | 3.3 | 4 | 5 | A | 3 | |
| Power-good output low voltage | PGLOW | 0.35 | V | 1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA | 4 | ||
| Precision EN input logic high | ENHIGH | 595 | 625 | 690 | mV | 1.1 V ≤ VIN ≤ 1.98 V | 4 |
| Precision EN input logic low | ENLOW | 550 | 580 | 630 | mV | 1.1 V ≤ VIN ≤ 1.98 V | 4 |
| Undervoltage lockout rising | UVLORISE | 1.01 | 1.06 | V | TJ = −40°C to +125°C | 4 | |
| Undervoltage lockout falling | UVLOFALL | 0.87 | 0.93 | V | TJ = −40°C to +125°C | 4 | |
| Input capacitance (recommended) | CIN | 7 | 10 | µF | TA = −40°C to +125°C | 4 | |
| Output capacitance (recommended) | COUT | 7 | 10 | µF | TA = −40°C to +125°C | 4 | |
| Regulator capacitance (recommended) | CREG | 0.7 | 1 | µF | TA = −40°C to +125°C | 4 | |
| Reference capacitance (recommended) | CREF | 0.7 | 1 | µF | TA = −40°C to +125°C | 4 | |
| Capacitor ESR (CIN, COUT) | RESR | 0.001 | 0.5 | Ω | TA = −40°C to +125°C | 4 | |
| Capacitor ESR (CREG, CREF) | RESR | 0.001 | 0.2 | Ω | TA = −40°C to +125°C | 4 | |
| VIN to GND | VIN | -0.3 | 2.16 | V | 5 | ||
| EN to GND | EN | -0.3 | 3.96 | V | 5 | ||
| VOUT to GND | VOUT | -0.3 | V | Upper limit printed as VIN | 5 | ||
| SENSE to GND | SENSE | -0.3 | V | Upper limit printed as VIN | 5 | ||
| VREG to GND | VREG | -0.3 | V | Upper limit printed as VIN | 5 | ||
| REFCAP to GND | REFCAP | -0.3 | V | Upper limit printed as VIN | 5 | ||
| VADJ to GND | VADJ | -0.3 | V | Upper limit printed as VIN | 5 | ||
| SS to GND | SS | -0.3 | V | Upper limit printed as VIN | 5 | ||
| PG to GND | PG | -0.3 | 3.96 | V | 5 | ||
| Operating temperature range | TA | -40 | 125 | °C | 5 | ||
| Operating junction temperature | TJ | 125 | °C | 5 | |||
| Lead temperature (soldering, 10 sec) | 300 | °C | Soldering, 10 sec | 5 | |||
| Thermal resistance junction to ambient, 16-lead LFCSP | θJA | 56 | °C/W | 4-layer 6400 mm² copper | 5 | ||
| Junction to board thermal characterization parameter, 16-lead LFCSP | ΨJB | 28.4 | °C/W | 4-layer 6400 mm² copper | 5 | ||
| Shutdown current | IGND-SD | 2 | µA | EN = GND | 3 | ||
| Noise spectral density | OUTNSD | 4 | nV/√Hz | VOUT = 0.9 V to 1.5 V, ILOAD = 100 mA, at 10 kHz | 3 | ||
| Noise spectral density | OUTNSD | 3 | nV/√Hz | VOUT = 0.9 V to 1.5 V, ILOAD = 100 mA, at 100 kHz | 3 | ||
| Adjustable output voltage gain factor | AD | 3 | TA = 25°C | 3 | |||
| Start-up time | tSTART-UP | 0.6 | ms | CSS = 10 nF, VOUT = 1.3 V | 3 | ||
| Thermal shutdown threshold | TSSD | 150 | °C | TJ rising | 4 | ||
| Thermal shutdown hysteresis | TSSD-HYS | 15 | °C | 4 | |||
| Power-good falling threshold | PGFALL | -7.5 | % | 1.1 V ≤ VIN ≤ 1.98 V | 4 | ||
| Power-good rising threshold | PGRISE | -5 | % | 1.1 V ≤ VIN ≤ 1.98 V | 4 | ||
| Power-good delay | PGDELAY | 0.75 | ms | ENRISING to PGRISING | 4 | ||
| Precision EN input hysteresis | ENHYS | 45 | mV | 4 | |||
| Precision EN input delay | tIEN-DLY | 100 | µs | From EN rising from 0 V to VIN to 0.1 × VOUT | 4 | ||
| Undervoltage lockout hysteresis | UVLOHYS | 80 | mV | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | copper to which the GND pin and the exposed pad (EPAD) of the | 15 |
CAD (KiCad official)
- Symbol:
ADP1763ACPZ-R7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
adp1763acpz-r7-etched.step/adp1763acpz-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp1763acpz-r7.step/adp1763acpz-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (18 pp, sha256
603a455c2dd7998c, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).