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ADP150AUJZ-1.8-R7

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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TSOT-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADP150AUJZ-1.8-R7

Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-5

ADP150AUJZ-1.8-R7 from Analog Devices, in a TSOT-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Regulator input supply, specified for 2.2 V to 5.5 V; bypass VIN to GND with a 1 µF or greater capacitor.
2 GND power_in Ground reference for the regulator.
3 EN input Enable input: drive high to turn the regulator on and low to turn it off; connect EN to VIN for automatic startup.
4 NC unconnected No connect; not connected internally.
5 VOUT power_out Regulated output voltage; bypass VOUT to GND with a 1 µF or greater capacitor.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSOT-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 2.2 5.5 V TJ = −40°C to +125°C 5
Output voltage accuracy (5-lead TSOT) VOUT -1 1 % IOUT = 10 mA 5
Output voltage accuracy over load and line (5-lead TSOT) VOUT -2.5 1.5 % 100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −40°C to +125°C 5
Line regulation ΔVOUT/ΔVIN -0.05 0.05 %/V VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −40°C to +125°C 5
Current limit threshold ILIMIT 190 260 400 mA 5
Absolute maximum VIN to GND VIN -0.3 6.5 V VIN to GND 7
Absolute maximum EN to GND EN -0.3 6.5 V EN to GND 7
Absolute maximum VOUT to GND VOUT -0.3 V VOUT to GND; upper limit printed as VIN 7
Storage temperature range TSTG -65 150 °C 7
Operating junction temperature range TJ -40 125 °C 7
Operating ambient temperature range TA -40 85 °C 7
Minimum input and output capacitance CMIN 0.7 µF TA = −40°C to +125°C 6
Capacitor ESR RESR 0.001 0.2 Ω TA = −40°C to +125°C 6
Thermal resistance junction-to-ambient, 5-lead TSOT θJA 170 °C/W 4-layer board 7
Junction-to-board thermal characterization, 5-lead TSOT ΨJB 43 °C/W 4-layer board 7
Operating supply current IGND 10 µA IOUT = 0 µA 5
Operating supply current IGND 22 µA IOUT = 0 µA, TJ = −40°C to +125°C 5
Operating supply current IGND 20 µA IOUT = 100 µA 5
Operating supply current IGND 40 µA IOUT = 100 µA, TJ = −40°C to +125°C 5
Operating supply current IGND 60 µA IOUT = 10 mA 5
Operating supply current IGND 100 µA IOUT = 10 mA, TJ = −40°C to +125°C 5
Operating supply current IGND 220 µA IOUT = 150 mA 5
Operating supply current IGND 320 µA IOUT = 150 mA, TJ = −40°C to +125°C 5
Shutdown current IGND-SD 0.2 µA EN = GND 5
Shutdown current IGND-SD 1 µA EN = GND, TJ = −40°C to +125°C 5
Load regulation (5-lead TSOT) ΔVOUT/ΔIOUT 0.003 %/mA IOUT = 100 µA to 150 mA 5
Load regulation (5-lead TSOT) ΔVOUT/ΔIOUT 0.0075 %/mA IOUT = 100 µA to 150 mA, TJ = −40°C to +125°C 5
Dropout voltage VDROPOUT 10 mV IOUT = 10 mA 5
Dropout voltage VDROPOUT 35 mV IOUT = 10 mA, TJ = −40°C to +125°C 5
Dropout voltage VDROPOUT 105 mV IOUT = 150 mA 5
Dropout voltage VDROPOUT 160 mV IOUT = 150 mA, TJ = −40°C to +125°C 5
Undervoltage lockout, input voltage rising UVLORISE 1.96 V TJ = −40°C to +125°C 5
Undervoltage lockout, input voltage falling UVLOFALL 1.28 V TJ = −40°C to +125°C 5
Undervoltage lockout hysteresis UVLOHYS 115 mV TJ = −40°C to +125°C 5
Thermal shutdown threshold TSSD 150 °C TJ rising 5
Thermal shutdown hysteresis TSSD-HYS 15 °C 5
EN input logic high VIH 1.2 V 2.2 V ≤ VIN ≤ 5.5 V 5
EN input logic low VIL 0.4 V 2.2 V ≤ VIN ≤ 5.5 V 5
EN input leakage current VI-LEAKAGE 0.001 µA EN = IN or GND 5
EN input leakage current VI-LEAKAGE 1 µA EN = IN or GND, TJ = −40°C to +125°C 5
Output noise (1.8 V option) OUTNOISE 9 µV rms 10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.8 V 5
Power supply rejection ratio (1.8 V option) PSRR 70 dB 10 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA (VIN = VOUT + 0.5 V) 6
Power supply rejection ratio (1.8 V option) PSRR 55 dB 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA (VIN = VOUT + 0.5 V) 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper typical θJA values of the 5-lead TSOT and 4-ball WLCSP packages for various PCB copper sizes. Table 8 shows the typical ΨJB 16

CAD (KiCad official)

  • Symbol: ADP150AUJZ-1.8-R7
  • Footprint: Package_TO_SOT_SMD:TSOT-23-5
  • 3D model: TSOT-5 (KiCad packages3D, STEP)
  • 3D model files: adp150aujz-1-8-r7-etched.step / adp150aujz-1-8-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adp150aujz-1-8-r7.step / adp150aujz-1-8-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 520c21304e4b84ec, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF