Adom Symbol

@@ -5,6 +5,16 @@ Standalone Rust CLI + live app for **KiCad schematic symbols**. Generates through the shared **service-kicad** container, and serves an AI-drivable live viewer with a full layout studio. No Node, no gallia, no local KiCad install. ++## Chip thumbnail in every symbol (default since 1.2.0)++`adom-symbol create` bakes a 3D-chip thumbnail into the middle of the symbol body as+real KiCad polylines: the part's real outline when chip-thumbnailer has rendered+`<mpn>-3d-outline-*-named.svg`, otherwise a generic isometric chip with the part name+lasered on top. Turn it off with `--no-chip-outline` (or `preferences.chipOutline:false`,+or `chipOutline:false` in `~/.claude/skills/adom/preferences.json`); size it with+`--chip-size large|medium|small`.+ ## Try it on any component page: the symbol-variants widget  ::adom-symbol-variants{src="/ray/ch340g/render/page.json" layout="sqg"}

@@ -41,10 +41,59 @@ try { |-----------|--------|--------| | `edaTool` | `kicad`, `fusion360`, `altium`, `cadence`, `tscircuit`, `easyeda`, `other` | Controls primary output format and delivery target | | `pinLayout` | `left-right`, `square`, `square-grouped`, `all-sides` | `left-right`: pins on left and right only (default Adom style, 2-column). `square`: package order walked like a QFP (pin 1 down the left, along the bottom, up the right, back across the top, ceil(n/4) per side; groups dropped). `square-grouped`: whole groups per side, Power on top, grounds split out onto the bottom as "Ground", the rest largest-first onto the emptiest side. `all-sides`: legacy name, behaves as `square-grouped` unless pins carry an explicit `side` |-| `chipNameCentered` | `true`, `false` | If true, add a centered text element with the chip name in the middle of the symbol body (vertically centered) so it's always visible even when zoomed out |+| `chipNameCentered` | `true`, `false` | If true, add a centered text element with the chip name in the middle of the symbol body (vertically centered) so it's always visible even when zoomed out. With the chip thumbnail on (the default) the name is lasered on the chip instead, never drawn twice |+| `chipOutline` | `true` (default), `false` | **The 3D-chip thumbnail baked into the symbol body.** `create` draws it by default as real `(polyline …)` geometry, so KiCad, adom-lbr/Fusion and Altium all show it: the part's real body when a chip-thumbnailer outline (`<mpn>-3d-outline-*-named.svg`) exists, else a generic isometric chip with the part name lasered on its top face. `false` = plain rectangle (also `--no-chip-outline` per call) |+| `chipSize` | `large` (default), `medium`, `small` | How much of the body the chip thumbnail fills (0.62 / 0.48 / 0.36 of the body). Also `--chip-size` per call | | `partNumber` | `none`, `mouser`, `digikey`, `jlcpcb` | If not "none", add a property field for the specified distributor's part number. Research and fill it in during Step 1 | | `deliveryTarget` | `webview`, `desktop`, `both` | `webview`: preview in Hydrogen webview first, only send to desktop when asked. `desktop`: send directly to desktop EDA after lint/validate pass. `both`: preview in Hydrogen webview AND send to desktop in parallel | +### The chip thumbnail is ON by default — do not ask, do not add a step++Since 1.2.0 `adom-symbol create` bakes the 3D-chip thumbnail into the middle of every IC+symbol on its own. There is nothing to request and no `render --iso` pass to run:++- **Source, in order:** `--outline-svg <file>` / `outlineSvg` in the create JSON →+  auto-discovered `<mpn>-3d-outline-{heavy,dark,hairline,teal}-named.svg` beside `--out`,+  beside the create JSON, in the cwd, or in `~/project/chip-fetcher/library/<mpn>/`+  (`$CHIP_FETCHER_LIBRARY`) → the built-in generic isometric chip (+ lasered name).+- **Where:** centred in the text-free lane between the pin-name columns (the same+  `icon_rect` the outline contract describes); a short 2-column body is grown on-grid+  so a readable icon (≥ 9 mm) fits. Under 9 mm the icon is omitted rather than blobbed.+- **Provenance:** a hidden `Adom_Chip_Outline` property (`generic-iso@large`,+  `asset:<file>@medium`, …). `render` sees it and never composites a second chip on top.+- **Off / size:** `--no-chip-outline`, `--chip-size small`, or `preferences.chipOutline`+  / `preferences.chipSize` in the create JSON, or `chipOutline` / `chipSize` in+  `~/.claude/skills/adom/preferences.json` (precedence: CLI flag > create JSON > global+  file > default ON/large). `--chip-outline` forces it on.+- The stdout of `create` says which source was baked. If it says *generic*, get the real+  body and re-run. **The STEP ladder (do this without being asked):**+  1. Manufacturer STEP via the desktop browser: WebFetch/curl are blocked by ST/TI/Mouser-class+     bot walls, so use pup with the site skill from `adom/electronics-sites-skillpack` (install it+     if missing). Sign in from pup's vault (`pup_login`); on first use seed the vault from the+     user's own browser with `pup_import_browser_logins {}` (one consent + one UAC is fine).+     **Drive any captcha yourself** — trusted click, vision on the image grid — never toast the+     user, never switch to the CDP lane (adom/pup-bridge#120 tracks the ext-lane verbs).+     Basic-Auth downloads (CSE family) come from the vault too (adom/pup-bridge#119).+  2. `chip-fetcher fetch <MPN>` runs that ladder (manufacturer → SnapMagic → Mouser → DigiKey → UL/CSE).+  3. No STEP obtainable, or the STEP won't convert? **Model it yourself** from the datasheet's+     outline drawing (CadQuery: cap, optical windows, marking, pin-1 mark; no engraved MPN) and ship+     that STEP. A library MUST carry a 3D body — the final board render needs it.+  Then `adom-chip-thumbnailer once <MPN>` makes the outline family and `create` bakes the real body.+  Never engrave the MPN into a STEP: the thumbnailer lasers it, and two names read as text-over-text.++**The check-and-revise loop (mandatory — the binary asks, the AI judges).** `create` ends+with `_hint:` lines. Follow them every time: rasterize the symbol SVG, LOOK at the chip in+the body, and decide whether the lasered part number landed on top of the chip's windows /+markings / other top-face features. The tool cannot see that; you can. If it did:++1. `--outline-svg <lib>/<MPN>-3d-outline-heavy.svg` (the un-named outline): adom-symbol+   then lasers the name UNDER the chip inside the icon box — always legible, never on the die.+2. or a smaller chip (`--chip-size medium|small`) when the collision is with pin names;+3. or, once chip-thumbnailer can laser on a side face, re-laser there and re-run `create`.++Re-run `create` after the revision and look again. Ship only when the thumbnail reads+cleanly. Report which source and placement you shipped in one line.+ ## KiCad Service  All service-kicad operations (SVG export, linting, STEP/GLB export) are served by **service-kicad** — the shared headless KiCad container. **Always shell out to the `service-kicad` CLI**, never call its HTTP endpoints directly:

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@@ -1,6 +1,6 @@ {   "slug": "adom-symbol",-  "version": "1.1.13",+  "version": "1.2.0",   "type": "app",   "description": "KiCad symbol creator with interactive viewer and delivery to KiCad/Fusion 360",   "dependencies": {@@ -54,4 +54,4 @@       "prompt": "open my RP2040.kicad_sym in the interactive symbol viewer"     }   ]-}\ No newline at end of file+}

@@ -1,6 +1,6 @@ {   "slug": "adom-symbol",-  "version": "1.1.13",+  "version": "1.2.0",   "type": "app",   "description": "KiCad symbol creator with interactive viewer and delivery to KiCad/Fusion 360",   "dependencies": {